ADMINISTRATION MODULE, PRODUCER AND CONSUMER PROCESSOR, ARRANGEMENT THEREOF AND METHOD FOR INTER-PROCESSOR COMMUNICATION VIA A SHARED MEMORY
Administration module (AM), producer (PP) and consumer processor (CP), arrangement thereof and method for inter-processor communication via a shared memory (SM), wherein said module (AM) comprises: means for storing (10) and administering (11) the states of triple-buffers (B0... Bm), each buffer (B0...
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| creator | ROETTGER, KAI HACIOGLU, HAMIT |
| description | Administration module (AM), producer (PP) and consumer processor (CP), arrangement thereof and method for inter-processor communication via a shared memory (SM), wherein said module (AM) comprises: means for storing (10) and administering (11) the states of triple-buffers (B0... Bm), each buffer (B0... Bm) having a read- (WSB), a write- (WSB) and an idle-sub-buffer (ISB); means for communicating (20) with at least one producer (PP) and at least one consumer processor (CP), and wherein said administration means (11) is formed to determine a targeted read- (RSB) or write-sub-buffer (WSB) from the triple-buffers (B0... Bm) in response to a producer or consumer processor access, respectively.
L'invention porte sur un module d'administration (AM), un producteur (PP) et le processeur grand public (CP), leur combinaison et sur une méthode de communication entre processeurs via une mémoire partagée (SM). Ledit module (AM) comprend: des moyens de stockage (10) et administration (11) des états de triples tampons (B0... Bm), chaque tampon (B0... Bm) comprenant: un sous-tampon de lecture (RSB), un sous-tampon d'écriture (WSB) et un sous-tampon de réserve (ISB); des moyens de communication (20) avec au moins le producteur (PP) et au moins le processeur grand public (CP). Ledit moyen d'administration (11) sert à déterminer un sous-tampon de lecture (RSB), et un sous-tampon d'écriture (WSB) des triples tampons (B0... Bm), en réponse à l'accès d'un producteur ou d'un processeur grand public. |
| format | Patent |
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L'invention porte sur un module d'administration (AM), un producteur (PP) et le processeur grand public (CP), leur combinaison et sur une méthode de communication entre processeurs via une mémoire partagée (SM). Ledit module (AM) comprend: des moyens de stockage (10) et administration (11) des états de triples tampons (B0... Bm), chaque tampon (B0... Bm) comprenant: un sous-tampon de lecture (RSB), un sous-tampon d'écriture (WSB) et un sous-tampon de réserve (ISB); des moyens de communication (20) avec au moins le producteur (PP) et au moins le processeur grand public (CP). Ledit moyen d'administration (11) sert à déterminer un sous-tampon de lecture (RSB), et un sous-tampon d'écriture (WSB) des triples tampons (B0... Bm), en réponse à l'accès d'un producteur ou d'un processeur grand public.</description><language>eng ; fre</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080814&DB=EPODOC&CC=WO&NR=2008095548A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080814&DB=EPODOC&CC=WO&NR=2008095548A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ROETTGER, KAI</creatorcontrib><creatorcontrib>HACIOGLU, HAMIT</creatorcontrib><title>ADMINISTRATION MODULE, PRODUCER AND CONSUMER PROCESSOR, ARRANGEMENT THEREOF AND METHOD FOR INTER-PROCESSOR COMMUNICATION VIA A SHARED MEMORY</title><description>Administration module (AM), producer (PP) and consumer processor (CP), arrangement thereof and method for inter-processor communication via a shared memory (SM), wherein said module (AM) comprises: means for storing (10) and administering (11) the states of triple-buffers (B0... Bm), each buffer (B0... Bm) having a read- (WSB), a write- (WSB) and an idle-sub-buffer (ISB); means for communicating (20) with at least one producer (PP) and at least one consumer processor (CP), and wherein said administration means (11) is formed to determine a targeted read- (RSB) or write-sub-buffer (WSB) from the triple-buffers (B0... Bm) in response to a producer or consumer processor access, respectively.
L'invention porte sur un module d'administration (AM), un producteur (PP) et le processeur grand public (CP), leur combinaison et sur une méthode de communication entre processeurs via une mémoire partagée (SM). Ledit module (AM) comprend: des moyens de stockage (10) et administration (11) des états de triples tampons (B0... Bm), chaque tampon (B0... Bm) comprenant: un sous-tampon de lecture (RSB), un sous-tampon d'écriture (WSB) et un sous-tampon de réserve (ISB); des moyens de communication (20) avec au moins le producteur (PP) et au moins le processeur grand public (CP). Ledit moyen d'administration (11) sert à déterminer un sous-tampon de lecture (RSB), et un sous-tampon d'écriture (WSB) des triples tampons (B0... Bm), en réponse à l'accès d'un producteur ou d'un processeur grand public.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNTbkKwkAQTWMh6j8M2CYQj0Ash83ELLg7MrtRrEKQtRIN6Gf40cYDa6t38I5h9MDCaKudF_SaLRgu6g3FsJWeKBJAW4Bi62rTi95V5BxLDCiCdk2GrAdfkRCX76whX3EBJQto60mSX6efMaa2Wn2edhoBwVUo9GoZlsM4Gpza8y1MvjiKpiV5VSWhuzbh1rXHcAn3Zs_zNM3TVZYtc5wt_ks9AZaoQM4</recordid><startdate>20080814</startdate><enddate>20080814</enddate><creator>ROETTGER, KAI</creator><creator>HACIOGLU, HAMIT</creator><scope>EVB</scope></search><sort><creationdate>20080814</creationdate><title>ADMINISTRATION MODULE, PRODUCER AND CONSUMER PROCESSOR, ARRANGEMENT THEREOF AND METHOD FOR INTER-PROCESSOR COMMUNICATION VIA A SHARED MEMORY</title><author>ROETTGER, KAI ; HACIOGLU, HAMIT</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO2008095548A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre</language><creationdate>2008</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>ROETTGER, KAI</creatorcontrib><creatorcontrib>HACIOGLU, HAMIT</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ROETTGER, KAI</au><au>HACIOGLU, HAMIT</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ADMINISTRATION MODULE, PRODUCER AND CONSUMER PROCESSOR, ARRANGEMENT THEREOF AND METHOD FOR INTER-PROCESSOR COMMUNICATION VIA A SHARED MEMORY</title><date>2008-08-14</date><risdate>2008</risdate><abstract>Administration module (AM), producer (PP) and consumer processor (CP), arrangement thereof and method for inter-processor communication via a shared memory (SM), wherein said module (AM) comprises: means for storing (10) and administering (11) the states of triple-buffers (B0... Bm), each buffer (B0... Bm) having a read- (WSB), a write- (WSB) and an idle-sub-buffer (ISB); means for communicating (20) with at least one producer (PP) and at least one consumer processor (CP), and wherein said administration means (11) is formed to determine a targeted read- (RSB) or write-sub-buffer (WSB) from the triple-buffers (B0... Bm) in response to a producer or consumer processor access, respectively.
L'invention porte sur un module d'administration (AM), un producteur (PP) et le processeur grand public (CP), leur combinaison et sur une méthode de communication entre processeurs via une mémoire partagée (SM). Ledit module (AM) comprend: des moyens de stockage (10) et administration (11) des états de triples tampons (B0... Bm), chaque tampon (B0... Bm) comprenant: un sous-tampon de lecture (RSB), un sous-tampon d'écriture (WSB) et un sous-tampon de réserve (ISB); des moyens de communication (20) avec au moins le producteur (PP) et au moins le processeur grand public (CP). Ledit moyen d'administration (11) sert à déterminer un sous-tampon de lecture (RSB), et un sous-tampon d'écriture (WSB) des triples tampons (B0... Bm), en réponse à l'accès d'un producteur ou d'un processeur grand public.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng ; fre |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | ADMINISTRATION MODULE, PRODUCER AND CONSUMER PROCESSOR, ARRANGEMENT THEREOF AND METHOD FOR INTER-PROCESSOR COMMUNICATION VIA A SHARED MEMORY |
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