CHIP SCALE PACKAGE AND METHOD OF ASSEMBLING THE SAME
A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, int...
Gespeichert in:
Hauptverfasser: | , , , , , |
---|---|
Format: | Patent |
Sprache: | eng ; fre |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | KOLAN, RAVI KANTH WANG, CHUEN KHIANG TAN, HIEN BOON CHONG, DESMOND YOK RUE BIDIN, RAHAMAT SUN, ANTHONY YI SHENG |
description | A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, into individual chip scale packages, each individual chip scale package including only one integrated circuit chip.
Procédé de fabrication d'un boîtier à l'échelle d'une puce. Ce procédé consiste à découper une tranche en plusieurs matrices de puce dont chacune comprend au moins deux puces à circuit intégré. Ledit procédé consiste également à monter chaque matrice sur un substrat et à découper chaque matrice, fixée au substrat, de manière à obtenir des boîtiers individuels à l'échelle d'une puce, chacun de ces boîtiers comprenant une seule puce à circuit intégré. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_WO2005053373A3</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>WO2005053373A3</sourcerecordid><originalsourceid>FETCH-epo_espacenet_WO2005053373A33</originalsourceid><addsrcrecordid>eNrjZDBx9vAMUAh2dvRxVQhwdPZ2dHdVcPRzUfB1DfHwd1Hwd1NwDA529XXy8fRzVwjxcFUIdvR15WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8eH-RgYGpgamxsbmxo7GxsSpAgAOFyeU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CHIP SCALE PACKAGE AND METHOD OF ASSEMBLING THE SAME</title><source>esp@cenet</source><creator>KOLAN, RAVI KANTH ; WANG, CHUEN KHIANG ; TAN, HIEN BOON ; CHONG, DESMOND YOK RUE ; BIDIN, RAHAMAT ; SUN, ANTHONY YI SHENG</creator><creatorcontrib>KOLAN, RAVI KANTH ; WANG, CHUEN KHIANG ; TAN, HIEN BOON ; CHONG, DESMOND YOK RUE ; BIDIN, RAHAMAT ; SUN, ANTHONY YI SHENG</creatorcontrib><description>A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, into individual chip scale packages, each individual chip scale package including only one integrated circuit chip.
Procédé de fabrication d'un boîtier à l'échelle d'une puce. Ce procédé consiste à découper une tranche en plusieurs matrices de puce dont chacune comprend au moins deux puces à circuit intégré. Ledit procédé consiste également à monter chaque matrice sur un substrat et à découper chaque matrice, fixée au substrat, de manière à obtenir des boîtiers individuels à l'échelle d'une puce, chacun de ces boîtiers comprenant une seule puce à circuit intégré.</description><language>eng ; fre</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20071221&DB=EPODOC&CC=WO&NR=2005053373A3$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25555,76308</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20071221&DB=EPODOC&CC=WO&NR=2005053373A3$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KOLAN, RAVI KANTH</creatorcontrib><creatorcontrib>WANG, CHUEN KHIANG</creatorcontrib><creatorcontrib>TAN, HIEN BOON</creatorcontrib><creatorcontrib>CHONG, DESMOND YOK RUE</creatorcontrib><creatorcontrib>BIDIN, RAHAMAT</creatorcontrib><creatorcontrib>SUN, ANTHONY YI SHENG</creatorcontrib><title>CHIP SCALE PACKAGE AND METHOD OF ASSEMBLING THE SAME</title><description>A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, into individual chip scale packages, each individual chip scale package including only one integrated circuit chip.
Procédé de fabrication d'un boîtier à l'échelle d'une puce. Ce procédé consiste à découper une tranche en plusieurs matrices de puce dont chacune comprend au moins deux puces à circuit intégré. Ledit procédé consiste également à monter chaque matrice sur un substrat et à découper chaque matrice, fixée au substrat, de manière à obtenir des boîtiers individuels à l'échelle d'une puce, chacun de ces boîtiers comprenant une seule puce à circuit intégré.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDBx9vAMUAh2dvRxVQhwdPZ2dHdVcPRzUfB1DfHwd1Hwd1NwDA529XXy8fRzVwjxcFUIdvR15WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8eH-RgYGpgamxsbmxo7GxsSpAgAOFyeU</recordid><startdate>20071221</startdate><enddate>20071221</enddate><creator>KOLAN, RAVI KANTH</creator><creator>WANG, CHUEN KHIANG</creator><creator>TAN, HIEN BOON</creator><creator>CHONG, DESMOND YOK RUE</creator><creator>BIDIN, RAHAMAT</creator><creator>SUN, ANTHONY YI SHENG</creator><scope>EVB</scope></search><sort><creationdate>20071221</creationdate><title>CHIP SCALE PACKAGE AND METHOD OF ASSEMBLING THE SAME</title><author>KOLAN, RAVI KANTH ; WANG, CHUEN KHIANG ; TAN, HIEN BOON ; CHONG, DESMOND YOK RUE ; BIDIN, RAHAMAT ; SUN, ANTHONY YI SHENG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO2005053373A33</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre</language><creationdate>2007</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KOLAN, RAVI KANTH</creatorcontrib><creatorcontrib>WANG, CHUEN KHIANG</creatorcontrib><creatorcontrib>TAN, HIEN BOON</creatorcontrib><creatorcontrib>CHONG, DESMOND YOK RUE</creatorcontrib><creatorcontrib>BIDIN, RAHAMAT</creatorcontrib><creatorcontrib>SUN, ANTHONY YI SHENG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KOLAN, RAVI KANTH</au><au>WANG, CHUEN KHIANG</au><au>TAN, HIEN BOON</au><au>CHONG, DESMOND YOK RUE</au><au>BIDIN, RAHAMAT</au><au>SUN, ANTHONY YI SHENG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CHIP SCALE PACKAGE AND METHOD OF ASSEMBLING THE SAME</title><date>2007-12-21</date><risdate>2007</risdate><abstract>A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, into individual chip scale packages, each individual chip scale package including only one integrated circuit chip.
Procédé de fabrication d'un boîtier à l'échelle d'une puce. Ce procédé consiste à découper une tranche en plusieurs matrices de puce dont chacune comprend au moins deux puces à circuit intégré. Ledit procédé consiste également à monter chaque matrice sur un substrat et à découper chaque matrice, fixée au substrat, de manière à obtenir des boîtiers individuels à l'échelle d'une puce, chacun de ces boîtiers comprenant une seule puce à circuit intégré.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng ; fre |
recordid | cdi_epo_espacenet_WO2005053373A3 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | CHIP SCALE PACKAGE AND METHOD OF ASSEMBLING THE SAME |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T21%3A08%3A35IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KOLAN,%20RAVI%20KANTH&rft.date=2007-12-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EWO2005053373A3%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |