A CONTROL ARCHITECTURE FOR A HIGH-THROUGHPUT MULTI-PROCESSOR CHANNEL DECODING SYSTEM

A multi-processor unit includes a first domain for processing data according to first configuration information and having multiple first domain processors each connected to communication apparatus and each performing a different function of the first processing. The first domain processors include...

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Bibliographische Detailangaben

1. Verfasser:	BURNS, GEOFFREY, F
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY PICTORIAL COMMUNICATION, e.g. TELEVISION
Online-Zugang:	Volltext bestellen
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