TRI-LAYER MASKING ARCHITECTURE FOR PATTERNING DUAL DAMASCENE INTERCONNECTS
This invention relates to a method of dual damascene integration for copper based wiring in a low-k dielectric stack (120, 130, 140) using three top hard mask layers (150, 160, 170) having alternating etch selectivity characteristics, and being, for example, inorganic/organic/inorganic. L'inven...
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| creator | TOWNSEND, PAUL, H., III MILLS, LYNNE, K STRITTMATTER, RICHARD, J WAETERLOOS, JOOST, J., M |
| description | This invention relates to a method of dual damascene integration for copper based wiring in a low-k dielectric stack (120, 130, 140) using three top hard mask layers (150, 160, 170) having alternating etch selectivity characteristics, and being, for example, inorganic/organic/inorganic.
L'invention concerne un procédé d'intégration de double damasquinage pour un câblage à base de cuivre dans un empilement à faible constante diélectrique (120, 130, 140). Ce procédé met en oeuvre trois couches supérieures rigides de masquage (150, 160, 170) qui présentent des caractéristiques de sélectivité de gravure alternantes, par exemple, inorganique/organique/inorganique. |
| format | Patent |
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L'invention concerne un procédé d'intégration de double damasquinage pour un câblage à base de cuivre dans un empilement à faible constante diélectrique (120, 130, 140). Ce procédé met en oeuvre trois couches supérieures rigides de masquage (150, 160, 170) qui présentent des caractéristiques de sélectivité de gravure alternantes, par exemple, inorganique/organique/inorganique.</description><edition>7</edition><language>eng ; fre</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20031016&DB=EPODOC&CC=WO&NR=03085724A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20031016&DB=EPODOC&CC=WO&NR=03085724A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TOWNSEND, PAUL, H., III</creatorcontrib><creatorcontrib>MILLS, LYNNE, K</creatorcontrib><creatorcontrib>STRITTMATTER, RICHARD, J</creatorcontrib><creatorcontrib>WAETERLOOS, JOOST, J., M</creatorcontrib><title>TRI-LAYER MASKING ARCHITECTURE FOR PATTERNING DUAL DAMASCENE INTERCONNECTS</title><description>This invention relates to a method of dual damascene integration for copper based wiring in a low-k dielectric stack (120, 130, 140) using three top hard mask layers (150, 160, 170) having alternating etch selectivity characteristics, and being, for example, inorganic/organic/inorganic.
L'invention concerne un procédé d'intégration de double damasquinage pour un câblage à base de cuivre dans un empilement à faible constante diélectrique (120, 130, 140). Ce procédé met en oeuvre trois couches supérieures rigides de masquage (150, 160, 170) qui présentent des caractéristiques de sélectivité de gravure alternantes, par exemple, inorganique/organique/inorganique.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPAKCfLU9XGMdA1S8HUM9vb0c1dwDHL28AxxdQ4JDXJVcPMPUghwDAlxDfIDybmEOvoouDgClTq7-rkqePoBJZz9_fyAqoN5GFjTEnOKU3mhNDeDoptriLOHbmpBfnxqcUFicmpeakl8uL-BsYGFqbmRiaOhMTFqAH9SLcY</recordid><startdate>20031016</startdate><enddate>20031016</enddate><creator>TOWNSEND, PAUL, H., III</creator><creator>MILLS, LYNNE, K</creator><creator>STRITTMATTER, RICHARD, J</creator><creator>WAETERLOOS, JOOST, J., M</creator><scope>EVB</scope></search><sort><creationdate>20031016</creationdate><title>TRI-LAYER MASKING ARCHITECTURE FOR PATTERNING DUAL DAMASCENE INTERCONNECTS</title><author>TOWNSEND, PAUL, H., III ; MILLS, LYNNE, K ; STRITTMATTER, RICHARD, J ; WAETERLOOS, JOOST, J., M</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO03085724A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre</language><creationdate>2003</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>TOWNSEND, PAUL, H., III</creatorcontrib><creatorcontrib>MILLS, LYNNE, K</creatorcontrib><creatorcontrib>STRITTMATTER, RICHARD, J</creatorcontrib><creatorcontrib>WAETERLOOS, JOOST, J., M</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TOWNSEND, PAUL, H., III</au><au>MILLS, LYNNE, K</au><au>STRITTMATTER, RICHARD, J</au><au>WAETERLOOS, JOOST, J., M</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>TRI-LAYER MASKING ARCHITECTURE FOR PATTERNING DUAL DAMASCENE INTERCONNECTS</title><date>2003-10-16</date><risdate>2003</risdate><abstract>This invention relates to a method of dual damascene integration for copper based wiring in a low-k dielectric stack (120, 130, 140) using three top hard mask layers (150, 160, 170) having alternating etch selectivity characteristics, and being, for example, inorganic/organic/inorganic.
L'invention concerne un procédé d'intégration de double damasquinage pour un câblage à base de cuivre dans un empilement à faible constante diélectrique (120, 130, 140). Ce procédé met en oeuvre trois couches supérieures rigides de masquage (150, 160, 170) qui présentent des caractéristiques de sélectivité de gravure alternantes, par exemple, inorganique/organique/inorganique.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | TRI-LAYER MASKING ARCHITECTURE FOR PATTERNING DUAL DAMASCENE INTERCONNECTS |
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