DUAL LAYER HARD MASK FOR EDRAM GATE ETCH PROCESS

A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes using a first material to establish a first hard mask pattern in only the first region and using a second material to establish a second ha...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: YU, CHIENFAN, WENSLEY, PAUL, DOBUZINSKY, DAVID, MARK, LIU, JOYCE, C, KHAN, BABAR, ALI
Format: Patent
Sprache:eng ; fre
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