Wafer level chip scale package having continuous through hole via configuration and fabrication method thereof

A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Fang, Li-Chih, Chung, Kee-Wei, Chang, Chia-Chang, Hsu, Hung-Hsin, Lien, Chia-Wen, Chang, Wen-Hsiung
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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