Method and apparatus for test time reduction using fractional data packing

An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan output...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Kawoosa, Mudasir Shafat, Singhal, Vivek, Potty, Sreenath Narayanan, Mittal, Rajesh
Format:	Patent
Sprache:	eng
Schlagworte:	MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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