Debug architecture

Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Barlow Stephen John, McDonald-Maier Klaus Dieter, Hopkins Andrew Brian Thomas, Banerjee Arnab
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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