Ternary content addressable memory (TCAM) for multi bit miss detect circuit

The present disclosure relates to a pre-charge circuit including a first inverter which receives an early pre-charge signal and outputs an inverted early pre-charge signal, a first gate which receives a late pre-charge signal and a match line output signal and outputs an AND output signal, and a sec...

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Hauptverfasser: Arsovski Igor, Butler Van D, Fragano Michael T, Houle Robert M, Patil Akhilesh
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creator Arsovski Igor
Butler Van D
Fragano Michael T
Houle Robert M
Patil Akhilesh
description The present disclosure relates to a pre-charge circuit including a first inverter which receives an early pre-charge signal and outputs an inverted early pre-charge signal, a first gate which receives a late pre-charge signal and a match line output signal and outputs an AND output signal, and a second gate which receives the inverted early pre-charge signal and the AND output signal and outputs an effective pre-charge signal.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9916896B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9916896B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9916896B13</originalsourceid><addsrcrecordid>eNqNyr0KwjAUhuEsDqLewxl1cChCMaMWRRAn41zS5CsE8lNyTgfvXgcvwOkdnnep7gY12_omV7IgC1nvK5jtEEEJqXxpa7rTY0djqZTmKIGGIJQCM3kInJAL1c1B1mox2sjY_LpSdL2Y7rbHVHrwZB0ypH89tW7ao27PzeGP5QOtJzSk</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Ternary content addressable memory (TCAM) for multi bit miss detect circuit</title><source>esp@cenet</source><creator>Arsovski Igor ; Butler Van D ; Fragano Michael T ; Houle Robert M ; Patil Akhilesh</creator><creatorcontrib>Arsovski Igor ; Butler Van D ; Fragano Michael T ; Houle Robert M ; Patil Akhilesh</creatorcontrib><description>The present disclosure relates to a pre-charge circuit including a first inverter which receives an early pre-charge signal and outputs an inverted early pre-charge signal, a first gate which receives a late pre-charge signal and a match line output signal and outputs an AND output signal, and a second gate which receives the inverted early pre-charge signal and the AND output signal and outputs an effective pre-charge signal.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20180313&amp;DB=EPODOC&amp;CC=US&amp;NR=9916896B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20180313&amp;DB=EPODOC&amp;CC=US&amp;NR=9916896B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Arsovski Igor</creatorcontrib><creatorcontrib>Butler Van D</creatorcontrib><creatorcontrib>Fragano Michael T</creatorcontrib><creatorcontrib>Houle Robert M</creatorcontrib><creatorcontrib>Patil Akhilesh</creatorcontrib><title>Ternary content addressable memory (TCAM) for multi bit miss detect circuit</title><description>The present disclosure relates to a pre-charge circuit including a first inverter which receives an early pre-charge signal and outputs an inverted early pre-charge signal, a first gate which receives a late pre-charge signal and a match line output signal and outputs an AND output signal, and a second gate which receives the inverted early pre-charge signal and the AND output signal and outputs an effective pre-charge signal.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyr0KwjAUhuEsDqLewxl1cChCMaMWRRAn41zS5CsE8lNyTgfvXgcvwOkdnnep7gY12_omV7IgC1nvK5jtEEEJqXxpa7rTY0djqZTmKIGGIJQCM3kInJAL1c1B1mox2sjY_LpSdL2Y7rbHVHrwZB0ypH89tW7ao27PzeGP5QOtJzSk</recordid><startdate>20180313</startdate><enddate>20180313</enddate><creator>Arsovski Igor</creator><creator>Butler Van D</creator><creator>Fragano Michael T</creator><creator>Houle Robert M</creator><creator>Patil Akhilesh</creator><scope>EVB</scope></search><sort><creationdate>20180313</creationdate><title>Ternary content addressable memory (TCAM) for multi bit miss detect circuit</title><author>Arsovski Igor ; Butler Van D ; Fragano Michael T ; Houle Robert M ; Patil Akhilesh</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9916896B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2018</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Arsovski Igor</creatorcontrib><creatorcontrib>Butler Van D</creatorcontrib><creatorcontrib>Fragano Michael T</creatorcontrib><creatorcontrib>Houle Robert M</creatorcontrib><creatorcontrib>Patil Akhilesh</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Arsovski Igor</au><au>Butler Van D</au><au>Fragano Michael T</au><au>Houle Robert M</au><au>Patil Akhilesh</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Ternary content addressable memory (TCAM) for multi bit miss detect circuit</title><date>2018-03-13</date><risdate>2018</risdate><abstract>The present disclosure relates to a pre-charge circuit including a first inverter which receives an early pre-charge signal and outputs an inverted early pre-charge signal, a first gate which receives a late pre-charge signal and a match line output signal and outputs an AND output signal, and a second gate which receives the inverted early pre-charge signal and the AND output signal and outputs an effective pre-charge signal.</abstract><oa>free_for_read</oa></addata></record>
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title Ternary content addressable memory (TCAM) for multi bit miss detect circuit
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-13T10%3A09%3A06IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Arsovski%20Igor&rft.date=2018-03-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9916896B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true