System and method for low latency communication

A system and method for low latency and higher bandwidth communication between a central processing unit (CPU) and an accelerator is disclosed. When the CPU updates a copy of data stored at a shared memory, the CPU also sends an "invalidate" command to a cache coherent interconnect (CCI)....

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Rosenband Daniel, Nordin Grace
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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