Non-volatile multi-level-cell memory with decoupled bits for higher performance and energy efficiency

A non-volatile multi-level cell ("MLC") memory device is disclosed. The memory device has an array of non-volatile memory cells, an array of non-volatile memory cells, with each non-volatile memory cell storing multiple groups of bits. A row buffer in the memory device has multiple buffer...

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Hauptverfasser:	Yoon Han Bin, Muralimanohar Naveen, Jouppi Norman Paul
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
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creator	Yoon Han Bin Muralimanohar Naveen Jouppi Norman Paul
description	A non-volatile multi-level cell ("MLC") memory device is disclosed. The memory device has an array of non-volatile memory cells, an array of non-volatile memory cells, with each non-volatile memory cell storing multiple groups of bits. A row buffer in the memory device has multiple buffer portions, each buffer portion storing one or more bits from the memory cells and having different read and write latencies and energies.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9852792B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9852792B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9852792B23</originalsourceid><addsrcrecordid>eNqNiz0OgkAUBmksjHqHd4FtMEZpJRorG7Um6_ItvOTtT5YFw-2l8ABWk0lm1gXuwaspiM4sIDdKZiWYIMpAhBxcSDN9OPfUwoQxClp6cx7IhkQ9dz0SRaTFnPYGpH1L8EjdTLCWDcObeVusrJYBux83BV0vz_qmEEODIWqzLLl5ParToTxW5bnc_5F8Ad3gP2U</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Non-volatile multi-level-cell memory with decoupled bits for higher performance and energy efficiency</title><source>esp@cenet</source><creator>Yoon Han Bin ; Muralimanohar Naveen ; Jouppi Norman Paul</creator><creatorcontrib>Yoon Han Bin ; Muralimanohar Naveen ; Jouppi Norman Paul</creatorcontrib><description>A non-volatile multi-level cell ("MLC") memory device is disclosed. The memory device has an array of non-volatile memory cells, an array of non-volatile memory cells, with each non-volatile memory cell storing multiple groups of bits. A row buffer in the memory device has multiple buffer portions, each buffer portion storing one or more bits from the memory cells and having different read and write latencies and energies.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20171226&DB=EPODOC&CC=US&NR=9852792B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20171226&DB=EPODOC&CC=US&NR=9852792B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Yoon Han Bin</creatorcontrib><creatorcontrib>Muralimanohar Naveen</creatorcontrib><creatorcontrib>Jouppi Norman Paul</creatorcontrib><title>Non-volatile multi-level-cell memory with decoupled bits for higher performance and energy efficiency</title><description>A non-volatile multi-level cell ("MLC") memory device is disclosed. The memory device has an array of non-volatile memory cells, an array of non-volatile memory cells, with each non-volatile memory cell storing multiple groups of bits. A row buffer in the memory device has multiple buffer portions, each buffer portion storing one or more bits from the memory cells and having different read and write latencies and energies.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNiz0OgkAUBmksjHqHd4FtMEZpJRorG7Um6_ItvOTtT5YFw-2l8ABWk0lm1gXuwaspiM4sIDdKZiWYIMpAhBxcSDN9OPfUwoQxClp6cx7IhkQ9dz0SRaTFnPYGpH1L8EjdTLCWDcObeVusrJYBux83BV0vz_qmEEODIWqzLLl5ParToTxW5bnc_5F8Ad3gP2U</recordid><startdate>20171226</startdate><enddate>20171226</enddate><creator>Yoon Han Bin</creator><creator>Muralimanohar Naveen</creator><creator>Jouppi Norman Paul</creator><scope>EVB</scope></search><sort><creationdate>20171226</creationdate><title>Non-volatile multi-level-cell memory with decoupled bits for higher performance and energy efficiency</title><author>Yoon Han Bin ; Muralimanohar Naveen ; Jouppi Norman Paul</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9852792B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Yoon Han Bin</creatorcontrib><creatorcontrib>Muralimanohar Naveen</creatorcontrib><creatorcontrib>Jouppi Norman Paul</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yoon Han Bin</au><au>Muralimanohar Naveen</au><au>Jouppi Norman Paul</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Non-volatile multi-level-cell memory with decoupled bits for higher performance and energy efficiency</title><date>2017-12-26</date><risdate>2017</risdate><abstract>A non-volatile multi-level cell ("MLC") memory device is disclosed. The memory device has an array of non-volatile memory cells, an array of non-volatile memory cells, with each non-volatile memory cell storing multiple groups of bits. A row buffer in the memory device has multiple buffer portions, each buffer portion storing one or more bits from the memory cells and having different read and write latencies and energies.</abstract><oa>free_for_read</oa></addata></record>
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
title	Non-volatile multi-level-cell memory with decoupled bits for higher performance and energy efficiency
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