PSOC architecture
A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an int...
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| creator | Mar Monte Snyder Warren S |
| description | A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an integrated circuit (chip) and the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the chip. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9843327B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9843327B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9843327B13</originalsourceid><addsrcrecordid>eNrjZBAMCPZ3VkgsSs7ILElNLiktSuVhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhwZYWJsbGRuZOhsZEKAEAfTIfKA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PSOC architecture</title><source>esp@cenet</source><creator>Mar Monte ; Snyder Warren S</creator><creatorcontrib>Mar Monte ; Snyder Warren S</creatorcontrib><description>A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an integrated circuit (chip) and the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the chip.</description><language>eng</language><subject>ANALOGUE COMPUTERS ; BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; GENERATION OF NOISE BY SUCH CIRCUITS ; GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING,BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN ANON-SWITCHING MANNER ; IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS ; PHYSICS ; PULSE TECHNIQUE ; RESONATORS</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20171212&DB=EPODOC&CC=US&NR=9843327B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20171212&DB=EPODOC&CC=US&NR=9843327B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Mar Monte</creatorcontrib><creatorcontrib>Snyder Warren S</creatorcontrib><title>PSOC architecture</title><description>A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an integrated circuit (chip) and the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the chip.</description><subject>ANALOGUE COMPUTERS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>GENERATION OF NOISE BY SUCH CIRCUITS</subject><subject>GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING,BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN ANON-SWITCHING MANNER</subject><subject>IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>RESONATORS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAMCPZ3VkgsSs7ILElNLiktSuVhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhwZYWJsbGRuZOhsZEKAEAfTIfKA</recordid><startdate>20171212</startdate><enddate>20171212</enddate><creator>Mar Monte</creator><creator>Snyder Warren S</creator><scope>EVB</scope></search><sort><creationdate>20171212</creationdate><title>PSOC architecture</title><author>Mar Monte ; Snyder Warren S</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9843327B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>ANALOGUE COMPUTERS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>GENERATION OF NOISE BY SUCH CIRCUITS</topic><topic>GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING,BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN ANON-SWITCHING MANNER</topic><topic>IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>RESONATORS</topic><toplevel>online_resources</toplevel><creatorcontrib>Mar Monte</creatorcontrib><creatorcontrib>Snyder Warren S</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Mar Monte</au><au>Snyder Warren S</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PSOC architecture</title><date>2017-12-12</date><risdate>2017</risdate><abstract>A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an integrated circuit (chip) and the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the chip.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng |
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| subjects | ANALOGUE COMPUTERS BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY GENERATION OF NOISE BY SUCH CIRCUITS GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING,BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN ANON-SWITCHING MANNER IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS PHYSICS PULSE TECHNIQUE RESONATORS |
| title | PSOC architecture |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T09%3A16%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Mar%20Monte&rft.date=2017-12-12&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9843327B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |