Chip stack cooling structure

An apparatus comprises a first die, a thermal cooler formed over at least a portion of the first die, a second die formed over at least a portion of the thermal cooler, and a plurality of through-silicon vias providing electrical connections between the first die and the second die. The thermal cool...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: Chainer Timothy J
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Chainer Timothy J
description An apparatus comprises a first die, a thermal cooler formed over at least a portion of the first die, a second die formed over at least a portion of the thermal cooler, and a plurality of through-silicon vias providing electrical connections between the first die and the second die. The thermal cooler comprises a plurality of fluid channels for fluid cooling of the first die and the second die, the plurality of fluid channels being formed horizontally through the thermal cooler. The plurality of through-silicon vias are formed vertically through the first die, the thermal cooler and the second die.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9818726B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9818726B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9818726B23</originalsourceid><addsrcrecordid>eNrjZJBxzsgsUCguSUzOVkjOz8_JzEsH8opKk0tKi1J5GFjTEnOKU3mhNDeDgptriLOHbmpBfnxqcUFicmpeakl8aLClhaGFuZGZk5ExEUoAaU8jvQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Chip stack cooling structure</title><source>esp@cenet</source><creator>Chainer Timothy J</creator><creatorcontrib>Chainer Timothy J</creatorcontrib><description>An apparatus comprises a first die, a thermal cooler formed over at least a portion of the first die, a second die formed over at least a portion of the thermal cooler, and a plurality of through-silicon vias providing electrical connections between the first die and the second die. The thermal cooler comprises a plurality of fluid channels for fluid cooling of the first die and the second die, the plurality of fluid channels being formed horizontally through the thermal cooler. The plurality of through-silicon vias are formed vertically through the first die, the thermal cooler and the second die.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20171114&amp;DB=EPODOC&amp;CC=US&amp;NR=9818726B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20171114&amp;DB=EPODOC&amp;CC=US&amp;NR=9818726B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Chainer Timothy J</creatorcontrib><title>Chip stack cooling structure</title><description>An apparatus comprises a first die, a thermal cooler formed over at least a portion of the first die, a second die formed over at least a portion of the thermal cooler, and a plurality of through-silicon vias providing electrical connections between the first die and the second die. The thermal cooler comprises a plurality of fluid channels for fluid cooling of the first die and the second die, the plurality of fluid channels being formed horizontally through the thermal cooler. The plurality of through-silicon vias are formed vertically through the first die, the thermal cooler and the second die.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJBxzsgsUCguSUzOVkjOz8_JzEsH8opKk0tKi1J5GFjTEnOKU3mhNDeDgptriLOHbmpBfnxqcUFicmpeakl8aLClhaGFuZGZk5ExEUoAaU8jvQ</recordid><startdate>20171114</startdate><enddate>20171114</enddate><creator>Chainer Timothy J</creator><scope>EVB</scope></search><sort><creationdate>20171114</creationdate><title>Chip stack cooling structure</title><author>Chainer Timothy J</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9818726B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Chainer Timothy J</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chainer Timothy J</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Chip stack cooling structure</title><date>2017-11-14</date><risdate>2017</risdate><abstract>An apparatus comprises a first die, a thermal cooler formed over at least a portion of the first die, a second die formed over at least a portion of the thermal cooler, and a plurality of through-silicon vias providing electrical connections between the first die and the second die. The thermal cooler comprises a plurality of fluid channels for fluid cooling of the first die and the second die, the plurality of fluid channels being formed horizontally through the thermal cooler. The plurality of through-silicon vias are formed vertically through the first die, the thermal cooler and the second die.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US9818726B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Chip stack cooling structure
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-15T11%3A53%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Chainer%20Timothy%20J&rft.date=2017-11-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9818726B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true