Lateral power integrated devices having low on-resistance

A lateral power integrated device includes a source region and a drain region disposed in a semiconductor layer and spaced apart from each other in a first direction, a drift region disposed in the semiconductor layer and surrounding the drain region, a channel region arranged between the source reg...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Lee Sang Hyun, Ko Kwang Sik, Park Joo Won
Format: Patent
Sprache:eng
Schlagworte:
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