Wafer rigidity with reinforcement structure

Wafer rigidity with reinforcement structure

Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias t...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Filippi Ronald G, Kim Andrew T, Kaltalioglu Erdem, Wang Ping-Chuan
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Filippi Ronald G
Kim Andrew T
Kaltalioglu Erdem
Wang Ping-Chuan
description Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9761539B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9761539B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9761539B23</originalsourceid><addsrcrecordid>eNrjZNAOT0xLLVIoykzPTMksqVQozyzJUChKzcxLyy9KTs1NzStRKC4pKk0uKS1K5WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHBluZmhqbGlk5GxkQoAQBX7ins</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Wafer rigidity with reinforcement structure</title><source>esp@cenet</source><creator>Filippi Ronald G ; Kim Andrew T ; Kaltalioglu Erdem ; Wang Ping-Chuan</creator><creatorcontrib>Filippi Ronald G ; Kim Andrew T ; Kaltalioglu Erdem ; Wang Ping-Chuan</creatorcontrib><description>Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170912&amp;DB=EPODOC&amp;CC=US&amp;NR=9761539B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170912&amp;DB=EPODOC&amp;CC=US&amp;NR=9761539B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Filippi Ronald G</creatorcontrib><creatorcontrib>Kim Andrew T</creatorcontrib><creatorcontrib>Kaltalioglu Erdem</creatorcontrib><creatorcontrib>Wang Ping-Chuan</creatorcontrib><title>Wafer rigidity with reinforcement structure</title><description>Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAOT0xLLVIoykzPTMksqVQozyzJUChKzcxLyy9KTs1NzStRKC4pKk0uKS1K5WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHBluZmhqbGlk5GxkQoAQBX7ins</recordid><startdate>20170912</startdate><enddate>20170912</enddate><creator>Filippi Ronald G</creator><creator>Kim Andrew T</creator><creator>Kaltalioglu Erdem</creator><creator>Wang Ping-Chuan</creator><scope>EVB</scope></search><sort><creationdate>20170912</creationdate><title>Wafer rigidity with reinforcement structure</title><author>Filippi Ronald G ; Kim Andrew T ; Kaltalioglu Erdem ; Wang Ping-Chuan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9761539B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Filippi Ronald G</creatorcontrib><creatorcontrib>Kim Andrew T</creatorcontrib><creatorcontrib>Kaltalioglu Erdem</creatorcontrib><creatorcontrib>Wang Ping-Chuan</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Filippi Ronald G</au><au>Kim Andrew T</au><au>Kaltalioglu Erdem</au><au>Wang Ping-Chuan</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Wafer rigidity with reinforcement structure</title><date>2017-09-12</date><risdate>2017</risdate><abstract>Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US9761539B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Wafer rigidity with reinforcement structure
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-05T08%3A22%3A53IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Filippi%20Ronald%20G&rft.date=2017-09-12&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9761539B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true