Semiconductor lead frame, semiconductor package, and manufacturing method thereof

A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for an internal terminal is provided around the semiconductor chip mounting area. A second plating layer for an external terminal is provided o...

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Hauptverfasser: Hishiki Kaoru, Iidani Ichinori
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creator Hishiki Kaoru
Iidani Ichinori
description A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for an internal terminal is provided around the semiconductor chip mounting area. A second plating layer for an external terminal is provided on a back surface of the metal plate at a location opposite to the semiconductor chip mounting area. The first plating layer includes a fall-off prevention structure for preventing the first plating layer from falling off from an encapsulating resin when the top surface of the metal plate is encapsulated in the encapsulating resin. The second plating layer does not include the fall-off prevention structure.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9735106B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9735106B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9735106B23</originalsourceid><addsrcrecordid>eNrjZAgMTs3NTM7PSylNLskvUshJTUxRSCtKzE3VUShGkSlITM5OTAcKJ-alKOQm5pWmJSaXlBZl5qUr5KaWZOSnKJRkpBal5qfxMLCmJeYUp_JCaW4GBTfXEGcP3dSC_PjUYqA5qXmpJfGhwZbmxqaGBmZORsZEKAEAkcQ3wA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor lead frame, semiconductor package, and manufacturing method thereof</title><source>esp@cenet</source><creator>Hishiki Kaoru ; Iidani Ichinori</creator><creatorcontrib>Hishiki Kaoru ; Iidani Ichinori</creatorcontrib><description>A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for an internal terminal is provided around the semiconductor chip mounting area. A second plating layer for an external terminal is provided on a back surface of the metal plate at a location opposite to the semiconductor chip mounting area. The first plating layer includes a fall-off prevention structure for preventing the first plating layer from falling off from an encapsulating resin when the top surface of the metal plate is encapsulated in the encapsulating resin. The second plating layer does not include the fall-off prevention structure.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170815&amp;DB=EPODOC&amp;CC=US&amp;NR=9735106B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170815&amp;DB=EPODOC&amp;CC=US&amp;NR=9735106B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Hishiki Kaoru</creatorcontrib><creatorcontrib>Iidani Ichinori</creatorcontrib><title>Semiconductor lead frame, semiconductor package, and manufacturing method thereof</title><description>A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for an internal terminal is provided around the semiconductor chip mounting area. A second plating layer for an external terminal is provided on a back surface of the metal plate at a location opposite to the semiconductor chip mounting area. The first plating layer includes a fall-off prevention structure for preventing the first plating layer from falling off from an encapsulating resin when the top surface of the metal plate is encapsulated in the encapsulating resin. The second plating layer does not include the fall-off prevention structure.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAgMTs3NTM7PSylNLskvUshJTUxRSCtKzE3VUShGkSlITM5OTAcKJ-alKOQm5pWmJSaXlBZl5qUr5KaWZOSnKJRkpBal5qfxMLCmJeYUp_JCaW4GBTfXEGcP3dSC_PjUYqA5qXmpJfGhwZbmxqaGBmZORsZEKAEAkcQ3wA</recordid><startdate>20170815</startdate><enddate>20170815</enddate><creator>Hishiki Kaoru</creator><creator>Iidani Ichinori</creator><scope>EVB</scope></search><sort><creationdate>20170815</creationdate><title>Semiconductor lead frame, semiconductor package, and manufacturing method thereof</title><author>Hishiki Kaoru ; Iidani Ichinori</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9735106B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Hishiki Kaoru</creatorcontrib><creatorcontrib>Iidani Ichinori</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hishiki Kaoru</au><au>Iidani Ichinori</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor lead frame, semiconductor package, and manufacturing method thereof</title><date>2017-08-15</date><risdate>2017</risdate><abstract>A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for an internal terminal is provided around the semiconductor chip mounting area. A second plating layer for an external terminal is provided on a back surface of the metal plate at a location opposite to the semiconductor chip mounting area. The first plating layer includes a fall-off prevention structure for preventing the first plating layer from falling off from an encapsulating resin when the top surface of the metal plate is encapsulated in the encapsulating resin. The second plating layer does not include the fall-off prevention structure.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Semiconductor lead frame, semiconductor package, and manufacturing method thereof
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-19T04%3A54%3A53IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Hishiki%20Kaoru&rft.date=2017-08-15&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9735106B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true