Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessing
In one embodiment, a computer-implemented method includes instructing two or more processors that are operating in a normal state of a symmetric multiprocessing (SMP) network to transition from the normal state to a slow state. The two or more processors reduce their frequencies to respective target...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Klapproth Kenneth D Drapala Garrett M Sonnelitter, III Robert J Fee Michael F |
| description | In one embodiment, a computer-implemented method includes instructing two or more processors that are operating in a normal state of a symmetric multiprocessing (SMP) network to transition from the normal state to a slow state. The two or more processors reduce their frequencies to respective target frequencies in a transitional state when transitioning from the normal state to the slow state. It is determined that the two or more processors have achieved their respective target frequencies for the slow state. The slow state is entered, responsive to this determination. Responsive to entering the slow state, a first processor of the two or more processors is instructed to send empty packets across an interconnect to compensate for a first greatest potential rate differential between the first processor and a remainder of the two or more processors during the slow state. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9734110B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9734110B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9734110B23</originalsourceid><addsrcrecordid>eNqNjLsKwkAQAK-xEPUf9gcCxghi6wt7tQ7HsUkWcrvn7qW4vzeFhaXVMDDM0vWXwj5SACscBhWWySAL-F_vFN8TciiQ1bNRJmEDYhioH6qE2olGzwHnS4yYdf7FacyUVAKaEfdrt-j8aLj5cuXgdn2e7xUmadGSD8iY29fjeGj2db097Zo_kg9ewEHc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessing</title><source>esp@cenet</source><creator>Klapproth Kenneth D ; Drapala Garrett M ; Sonnelitter, III Robert J ; Fee Michael F</creator><creatorcontrib>Klapproth Kenneth D ; Drapala Garrett M ; Sonnelitter, III Robert J ; Fee Michael F</creatorcontrib><description>In one embodiment, a computer-implemented method includes instructing two or more processors that are operating in a normal state of a symmetric multiprocessing (SMP) network to transition from the normal state to a slow state. The two or more processors reduce their frequencies to respective target frequencies in a transitional state when transitioning from the normal state to the slow state. It is determined that the two or more processors have achieved their respective target frequencies for the slow state. The slow state is entered, responsive to this determination. Responsive to entering the slow state, a first processor of the two or more processors is instructed to send empty packets across an interconnect to compensate for a first greatest potential rate differential between the first processor and a remainder of the two or more processors during the slow state.</description><language>eng</language><subject>CALCULATING ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PHYSICS ; PRINTED CIRCUITS</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170815&DB=EPODOC&CC=US&NR=9734110B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170815&DB=EPODOC&CC=US&NR=9734110B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Klapproth Kenneth D</creatorcontrib><creatorcontrib>Drapala Garrett M</creatorcontrib><creatorcontrib>Sonnelitter, III Robert J</creatorcontrib><creatorcontrib>Fee Michael F</creatorcontrib><title>Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessing</title><description>In one embodiment, a computer-implemented method includes instructing two or more processors that are operating in a normal state of a symmetric multiprocessing (SMP) network to transition from the normal state to a slow state. The two or more processors reduce their frequencies to respective target frequencies in a transitional state when transitioning from the normal state to the slow state. It is determined that the two or more processors have achieved their respective target frequencies for the slow state. The slow state is entered, responsive to this determination. Responsive to entering the slow state, a first processor of the two or more processors is instructed to send empty packets across an interconnect to compensate for a first greatest potential rate differential between the first processor and a remainder of the two or more processors during the slow state.</description><subject>CALCULATING</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PHYSICS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjLsKwkAQAK-xEPUf9gcCxghi6wt7tQ7HsUkWcrvn7qW4vzeFhaXVMDDM0vWXwj5SACscBhWWySAL-F_vFN8TciiQ1bNRJmEDYhioH6qE2olGzwHnS4yYdf7FacyUVAKaEfdrt-j8aLj5cuXgdn2e7xUmadGSD8iY29fjeGj2db097Zo_kg9ewEHc</recordid><startdate>20170815</startdate><enddate>20170815</enddate><creator>Klapproth Kenneth D</creator><creator>Drapala Garrett M</creator><creator>Sonnelitter, III Robert J</creator><creator>Fee Michael F</creator><scope>EVB</scope></search><sort><creationdate>20170815</creationdate><title>Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessing</title><author>Klapproth Kenneth D ; Drapala Garrett M ; Sonnelitter, III Robert J ; Fee Michael F</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9734110B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>CALCULATING</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PHYSICS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>Klapproth Kenneth D</creatorcontrib><creatorcontrib>Drapala Garrett M</creatorcontrib><creatorcontrib>Sonnelitter, III Robert J</creatorcontrib><creatorcontrib>Fee Michael F</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Klapproth Kenneth D</au><au>Drapala Garrett M</au><au>Sonnelitter, III Robert J</au><au>Fee Michael F</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessing</title><date>2017-08-15</date><risdate>2017</risdate><abstract>In one embodiment, a computer-implemented method includes instructing two or more processors that are operating in a normal state of a symmetric multiprocessing (SMP) network to transition from the normal state to a slow state. The two or more processors reduce their frequencies to respective target frequencies in a transitional state when transitioning from the normal state to the slow state. It is determined that the two or more processors have achieved their respective target frequencies for the slow state. The slow state is entered, responsive to this determination. Responsive to entering the slow state, a first processor of the two or more processors is instructed to send empty packets across an interconnect to compensate for a first greatest potential rate differential between the first processor and a remainder of the two or more processors during the slow state.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US9734110B2 |
| source | esp@cenet |
| subjects | CALCULATING CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PHYSICS PRINTED CIRCUITS |
| title | Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessing |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-02T13%3A27%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Klapproth%20Kenneth%20D&rft.date=2017-08-15&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9734110B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |