Write driver and level shifter having shared transistors

Write driver and level shifter having shared transistors

A circuit includes: a first data line; a second data line; a write driver including first and second transistors; a first switch connected in series with the first transistor to form a first series-connected pair; a second switch in series with the second transistor to form a second series-connected...

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Hauptverfasser: Lee Cheng Hung, Yang Hao-I, Yang Jung-Ping, Huang Chia-En, Lin Geng-Cing
Format: Patent
Sprache:eng
Schlagworte:
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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creator Lee Cheng Hung
Yang Hao-I
Yang Jung-Ping
Huang Chia-En
Lin Geng-Cing
description A circuit includes: a first data line; a second data line; a write driver including first and second transistors; a first switch connected in series with the first transistor to form a first series-connected pair; a second switch in series with the second transistor to form a second series-connected pair; and a level shifter which includes the first and second transistors. The first series-connected pair is coupled between a first voltage node and the first data line. The second series-connected pair is coupled between the first voltage node and the second data line. Gate terminals of the first and second transistors are correspondingly cross-coupled with the second and first data lines.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9721651B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9721651B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9721651B23</originalsourceid><addsrcrecordid>eNrjZLAIL8osSVVIKcosSy1SSMxLUchJLUvNUSjOyEwrAYpkJJZl5qUDuYlFqSkKJUWJecWZxSX5RcU8DKxpiTnFqbxQmptBwc01xNlDN7UgPz61uCAxOTUvtSQ-NNjS3MjQzNTQyciYCCUAzUkuZg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Write driver and level shifter having shared transistors</title><source>esp@cenet</source><creator>Lee Cheng Hung ; Yang Hao-I ; Yang Jung-Ping ; Huang Chia-En ; Lin Geng-Cing</creator><creatorcontrib>Lee Cheng Hung ; Yang Hao-I ; Yang Jung-Ping ; Huang Chia-En ; Lin Geng-Cing</creatorcontrib><description>A circuit includes: a first data line; a second data line; a write driver including first and second transistors; a first switch connected in series with the first transistor to form a first series-connected pair; a second switch in series with the second transistor to form a second series-connected pair; and a level shifter which includes the first and second transistors. The first series-connected pair is coupled between a first voltage node and the first data line. The second series-connected pair is coupled between the first voltage node and the second data line. Gate terminals of the first and second transistors are correspondingly cross-coupled with the second and first data lines.</description><language>eng</language><subject>ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170801&amp;DB=EPODOC&amp;CC=US&amp;NR=9721651B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170801&amp;DB=EPODOC&amp;CC=US&amp;NR=9721651B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lee Cheng Hung</creatorcontrib><creatorcontrib>Yang Hao-I</creatorcontrib><creatorcontrib>Yang Jung-Ping</creatorcontrib><creatorcontrib>Huang Chia-En</creatorcontrib><creatorcontrib>Lin Geng-Cing</creatorcontrib><title>Write driver and level shifter having shared transistors</title><description>A circuit includes: a first data line; a second data line; a write driver including first and second transistors; a first switch connected in series with the first transistor to form a first series-connected pair; a second switch in series with the second transistor to form a second series-connected pair; and a level shifter which includes the first and second transistors. The first series-connected pair is coupled between a first voltage node and the first data line. The second series-connected pair is coupled between the first voltage node and the second data line. Gate terminals of the first and second transistors are correspondingly cross-coupled with the second and first data lines.</description><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAIL8osSVVIKcosSy1SSMxLUchJLUvNUSjOyEwrAYpkJJZl5qUDuYlFqSkKJUWJecWZxSX5RcU8DKxpiTnFqbxQmptBwc01xNlDN7UgPz61uCAxOTUvtSQ-NNjS3MjQzNTQyciYCCUAzUkuZg</recordid><startdate>20170801</startdate><enddate>20170801</enddate><creator>Lee Cheng Hung</creator><creator>Yang Hao-I</creator><creator>Yang Jung-Ping</creator><creator>Huang Chia-En</creator><creator>Lin Geng-Cing</creator><scope>EVB</scope></search><sort><creationdate>20170801</creationdate><title>Write driver and level shifter having shared transistors</title><author>Lee Cheng Hung ; Yang Hao-I ; Yang Jung-Ping ; Huang Chia-En ; Lin Geng-Cing</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9721651B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Lee Cheng Hung</creatorcontrib><creatorcontrib>Yang Hao-I</creatorcontrib><creatorcontrib>Yang Jung-Ping</creatorcontrib><creatorcontrib>Huang Chia-En</creatorcontrib><creatorcontrib>Lin Geng-Cing</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lee Cheng Hung</au><au>Yang Hao-I</au><au>Yang Jung-Ping</au><au>Huang Chia-En</au><au>Lin Geng-Cing</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Write driver and level shifter having shared transistors</title><date>2017-08-01</date><risdate>2017</risdate><abstract>A circuit includes: a first data line; a second data line; a write driver including first and second transistors; a first switch connected in series with the first transistor to form a first series-connected pair; a second switch in series with the second transistor to form a second series-connected pair; and a level shifter which includes the first and second transistors. The first series-connected pair is coupled between a first voltage node and the first data line. The second series-connected pair is coupled between the first voltage node and the second data line. Gate terminals of the first and second transistors are correspondingly cross-coupled with the second and first data lines.</abstract><oa>free_for_read</oa></addata></record>
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subjects ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
title Write driver and level shifter having shared transistors
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-23T21%3A55%3A38IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Lee%20Cheng%20Hung&rft.date=2017-08-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9721651B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true