Hierarchical wire-pin co-optimization

A method and system to perform physical synthesis in a chip design process using hierarchical wire-pin co-optimization are described. The method includes providing boundary conditions to each of a plurality of macros of the chip design from a unit level controller, the boundary conditions including...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Saha Sourav, Berry Christopher J, Chandrasekaran Ajith Kumar M, Ramji Shyam, Darden Randall J
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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