Multi-bit flip-flop with soft error suppression

A multi-bit flip-flop includes at least two storage stages. Each of the storage stages includes redundant latches to suppress state corruptions resulting from soft error upset at the storage stage. In addition, the multi-bit flip-flop includes a split clock path that routes different shared clock si...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Semenov Mikhail Yurievich, Mikhailov Victor Mikhailovich, Kornilov Alexander Ivanovich, Tipple David Russell
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE
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