Method for making electronic device with cover layer with openings and related devices
A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method a...
Gespeichert in:
Hauptverfasser: | , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Rendek, Jr. Louis Joseph Kerby Travis L Rodriguez Casey Philip Weatherspoon Michael Raymond |
description | A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method also includes positioning an IC on the cover layer so that bond pads of the IC are aligned with the openings, and heating under pressure the cover layer to both mechanically secure and electrically interconnect the IC. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9681543B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9681543B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9681543B23</originalsourceid><addsrcrecordid>eNrjZAjzTS3JyE9RSMsvUshNzM7MS1dIzUlNLinKz8tMVkhJLctMTlUozyzJUEjOL0stUshJrASSYIH8gtQ8oPpihcS8FIWi1JzEktQUqI5iHgbWtMSc4lReKM3NoODmGuLsoZtakB-fWlyQmJyal1oSHxpsaWZhaGpi7GRkTIQSAKstOVw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for making electronic device with cover layer with openings and related devices</title><source>esp@cenet</source><creator>Rendek, Jr. Louis Joseph ; Kerby Travis L ; Rodriguez Casey Philip ; Weatherspoon Michael Raymond</creator><creatorcontrib>Rendek, Jr. Louis Joseph ; Kerby Travis L ; Rodriguez Casey Philip ; Weatherspoon Michael Raymond</creatorcontrib><description>A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method also includes positioning an IC on the cover layer so that bond pads of the IC are aligned with the openings, and heating under pressure the cover layer to both mechanically secure and electrically interconnect the IC.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170613&DB=EPODOC&CC=US&NR=9681543B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170613&DB=EPODOC&CC=US&NR=9681543B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Rendek, Jr. Louis Joseph</creatorcontrib><creatorcontrib>Kerby Travis L</creatorcontrib><creatorcontrib>Rodriguez Casey Philip</creatorcontrib><creatorcontrib>Weatherspoon Michael Raymond</creatorcontrib><title>Method for making electronic device with cover layer with openings and related devices</title><description>A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method also includes positioning an IC on the cover layer so that bond pads of the IC are aligned with the openings, and heating under pressure the cover layer to both mechanically secure and electrically interconnect the IC.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAjzTS3JyE9RSMsvUshNzM7MS1dIzUlNLinKz8tMVkhJLctMTlUozyzJUEjOL0stUshJrASSYIH8gtQ8oPpihcS8FIWi1JzEktQUqI5iHgbWtMSc4lReKM3NoODmGuLsoZtakB-fWlyQmJyal1oSHxpsaWZhaGpi7GRkTIQSAKstOVw</recordid><startdate>20170613</startdate><enddate>20170613</enddate><creator>Rendek, Jr. Louis Joseph</creator><creator>Kerby Travis L</creator><creator>Rodriguez Casey Philip</creator><creator>Weatherspoon Michael Raymond</creator><scope>EVB</scope></search><sort><creationdate>20170613</creationdate><title>Method for making electronic device with cover layer with openings and related devices</title><author>Rendek, Jr. Louis Joseph ; Kerby Travis L ; Rodriguez Casey Philip ; Weatherspoon Michael Raymond</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9681543B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Rendek, Jr. Louis Joseph</creatorcontrib><creatorcontrib>Kerby Travis L</creatorcontrib><creatorcontrib>Rodriguez Casey Philip</creatorcontrib><creatorcontrib>Weatherspoon Michael Raymond</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Rendek, Jr. Louis Joseph</au><au>Kerby Travis L</au><au>Rodriguez Casey Philip</au><au>Weatherspoon Michael Raymond</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for making electronic device with cover layer with openings and related devices</title><date>2017-06-13</date><risdate>2017</risdate><abstract>A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method also includes positioning an IC on the cover layer so that bond pads of the IC are aligned with the openings, and heating under pressure the cover layer to both mechanically secure and electrically interconnect the IC.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US9681543B2 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
title | Method for making electronic device with cover layer with openings and related devices |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-24T19%3A35%3A36IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Rendek,%20Jr.%20Louis%20Joseph&rft.date=2017-06-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9681543B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |