Synchronizing a translation lookaside buffer with an extended paging table

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookas...

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Hauptverfasser:	Neiger Gilbert, Anderson Andrew V, Bennett Steven M, Uhlig Richard A, Schoenberg Sebastian, Sankaran Rajesh M, Rodgers Scott Dion, Rust Camron
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	Neiger Gilbert Anderson Andrew V Bennett Steven M Uhlig Richard A Schoenberg Sebastian Sankaran Rajesh M Rodgers Scott Dion Rust Camron
description	A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	Synchronizing a translation lookaside buffer with an extended paging table
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