System and method for reducing false preamble detection in a communication receiver

System and method for reducing false preamble detection in a communication receiver

An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that prod...

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Hauptverfasser: Khan Muhammad Kalimuddin, Quinlan Philip P. E, O'Mahony Shane, Mulvaney Kenneth J
Format: Patent
Sprache:eng
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ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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creator Khan Muhammad Kalimuddin
Quinlan Philip P. E
O'Mahony Shane
Mulvaney Kenneth J
description An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.
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subjects ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title System and method for reducing false preamble detection in a communication receiver
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