Flip-flop with reduced retention voltage

A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Patel Prayag Bhanubhai, Shah Jay Madhukar, Bapat Sachin, Rasouli Seid Hadi, Parkar Peeyush Kumar, Saint-Laurent Martin, Abu-Rahma Mohamed Hassan, Vilangudipitchai Ramaprasath, Datta Animesh
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE
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