Power domain aware insertion methods and designs for testing and repairing memory

Aspects of the present disclosure involve insertion of power domain aware memory testing logic into integrated circuit designs to enable efficient testing of the memories embedded therein. In example embodiments, each power domain of the integrated circuit, and the memories included therein, are ass...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Gregor Steven Lee, Arora Puneet, Kaushik Navneet, Card Norman
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS STATIC STORES TESTING
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