Integration of photonic, electronic, and sensor devices with SOI VLSI microprocessor technology
According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI stru...
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| creator | Babakhani Aydin Cordes Steven A Plouchart Jean-Olivier Sorce Peter J Reynolds Scott K Trzcinski Robert E |
| description | According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9632251B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9632251B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9632251B23</originalsourceid><addsrcrecordid>eNqNikEKwjAQAHPxIOof9gF6MEXBa0WxIHioei1hu20DcTcki-LvVfQBnmZgZmyaipX65NQLg3QQB1Fhj3OgQKjp645byMRZErR090gZHl4HqE8VXI91BTePSWKSd_lMSjiwBOmfUzPqXMg0-3FiYL87bw8LitJQjg6JSZtLvVkX1q6WpS3-WF7k-Dx4</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Integration of photonic, electronic, and sensor devices with SOI VLSI microprocessor technology</title><source>esp@cenet</source><creator>Babakhani Aydin ; Cordes Steven A ; Plouchart Jean-Olivier ; Sorce Peter J ; Reynolds Scott K ; Trzcinski Robert E</creator><creatorcontrib>Babakhani Aydin ; Cordes Steven A ; Plouchart Jean-Olivier ; Sorce Peter J ; Reynolds Scott K ; Trzcinski Robert E</creatorcontrib><description>According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; DEVICES USING STIMULATED EMISSION ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS ; OPTICS ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170425&DB=EPODOC&CC=US&NR=9632251B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170425&DB=EPODOC&CC=US&NR=9632251B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Babakhani Aydin</creatorcontrib><creatorcontrib>Cordes Steven A</creatorcontrib><creatorcontrib>Plouchart Jean-Olivier</creatorcontrib><creatorcontrib>Sorce Peter J</creatorcontrib><creatorcontrib>Reynolds Scott K</creatorcontrib><creatorcontrib>Trzcinski Robert E</creatorcontrib><title>Integration of photonic, electronic, and sensor devices with SOI VLSI microprocessor technology</title><description>According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>DEVICES USING STIMULATED EMISSION</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS</subject><subject>OPTICS</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNikEKwjAQAHPxIOof9gF6MEXBa0WxIHioei1hu20DcTcki-LvVfQBnmZgZmyaipX65NQLg3QQB1Fhj3OgQKjp645byMRZErR090gZHl4HqE8VXI91BTePSWKSd_lMSjiwBOmfUzPqXMg0-3FiYL87bw8LitJQjg6JSZtLvVkX1q6WpS3-WF7k-Dx4</recordid><startdate>20170425</startdate><enddate>20170425</enddate><creator>Babakhani Aydin</creator><creator>Cordes Steven A</creator><creator>Plouchart Jean-Olivier</creator><creator>Sorce Peter J</creator><creator>Reynolds Scott K</creator><creator>Trzcinski Robert E</creator><scope>EVB</scope></search><sort><creationdate>20170425</creationdate><title>Integration of photonic, electronic, and sensor devices with SOI VLSI microprocessor technology</title><author>Babakhani Aydin ; Cordes Steven A ; Plouchart Jean-Olivier ; Sorce Peter J ; Reynolds Scott K ; Trzcinski Robert E</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9632251B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>DEVICES USING STIMULATED EMISSION</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS</topic><topic>OPTICS</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Babakhani Aydin</creatorcontrib><creatorcontrib>Cordes Steven A</creatorcontrib><creatorcontrib>Plouchart Jean-Olivier</creatorcontrib><creatorcontrib>Sorce Peter J</creatorcontrib><creatorcontrib>Reynolds Scott K</creatorcontrib><creatorcontrib>Trzcinski Robert E</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Babakhani Aydin</au><au>Cordes Steven A</au><au>Plouchart Jean-Olivier</au><au>Sorce Peter J</au><au>Reynolds Scott K</au><au>Trzcinski Robert E</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integration of photonic, electronic, and sensor devices with SOI VLSI microprocessor technology</title><date>2017-04-25</date><risdate>2017</risdate><abstract>According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS DEVICES USING STIMULATED EMISSION ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS OPTICS PHYSICS SEMICONDUCTOR DEVICES |
| title | Integration of photonic, electronic, and sensor devices with SOI VLSI microprocessor technology |
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