Self-aligned dielectric isolation for FinFET devices
Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height...
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| creator | Bergendahl Marc Adam Standaert Theodorus Eduardus Yang Chih-Chao Cheng Kangguo Cai Xiuyu Xie Ruilong Koburger, III Charles William Horak David Vaclav Khakifirooz Ali Ponoth Shom |
| description | Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9627377B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9627377B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9627377B23</originalsourceid><addsrcrecordid>eNrjZDAJTs1J003MyUzPS01RSMlMzUlNLinKTFbILM7PSSzJzM9TSMsvUnDLzHNzDVFISS3LTE4t5mFgTUvMKU7lhdLcDApAWWcP3dSC_PjU4oLE5NS81JL40GBLMyNzY3NzJyNjIpQAALYQLDo</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Self-aligned dielectric isolation for FinFET devices</title><source>esp@cenet</source><creator>Bergendahl Marc Adam ; Standaert Theodorus Eduardus ; Yang Chih-Chao ; Cheng Kangguo ; Cai Xiuyu ; Xie Ruilong ; Koburger, III Charles William ; Horak David Vaclav ; Khakifirooz Ali ; Ponoth Shom</creator><creatorcontrib>Bergendahl Marc Adam ; Standaert Theodorus Eduardus ; Yang Chih-Chao ; Cheng Kangguo ; Cai Xiuyu ; Xie Ruilong ; Koburger, III Charles William ; Horak David Vaclav ; Khakifirooz Ali ; Ponoth Shom</creatorcontrib><description>Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170418&DB=EPODOC&CC=US&NR=9627377B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170418&DB=EPODOC&CC=US&NR=9627377B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Bergendahl Marc Adam</creatorcontrib><creatorcontrib>Standaert Theodorus Eduardus</creatorcontrib><creatorcontrib>Yang Chih-Chao</creatorcontrib><creatorcontrib>Cheng Kangguo</creatorcontrib><creatorcontrib>Cai Xiuyu</creatorcontrib><creatorcontrib>Xie Ruilong</creatorcontrib><creatorcontrib>Koburger, III Charles William</creatorcontrib><creatorcontrib>Horak David Vaclav</creatorcontrib><creatorcontrib>Khakifirooz Ali</creatorcontrib><creatorcontrib>Ponoth Shom</creatorcontrib><title>Self-aligned dielectric isolation for FinFET devices</title><description>Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAJTs1J003MyUzPS01RSMlMzUlNLinKTFbILM7PSSzJzM9TSMsvUnDLzHNzDVFISS3LTE4t5mFgTUvMKU7lhdLcDApAWWcP3dSC_PjU4oLE5NS81JL40GBLMyNzY3NzJyNjIpQAALYQLDo</recordid><startdate>20170418</startdate><enddate>20170418</enddate><creator>Bergendahl Marc Adam</creator><creator>Standaert Theodorus Eduardus</creator><creator>Yang Chih-Chao</creator><creator>Cheng Kangguo</creator><creator>Cai Xiuyu</creator><creator>Xie Ruilong</creator><creator>Koburger, III Charles William</creator><creator>Horak David Vaclav</creator><creator>Khakifirooz Ali</creator><creator>Ponoth Shom</creator><scope>EVB</scope></search><sort><creationdate>20170418</creationdate><title>Self-aligned dielectric isolation for FinFET devices</title><author>Bergendahl Marc Adam ; Standaert Theodorus Eduardus ; Yang Chih-Chao ; Cheng Kangguo ; Cai Xiuyu ; Xie Ruilong ; Koburger, III Charles William ; Horak David Vaclav ; Khakifirooz Ali ; Ponoth Shom</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9627377B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Bergendahl Marc Adam</creatorcontrib><creatorcontrib>Standaert Theodorus Eduardus</creatorcontrib><creatorcontrib>Yang Chih-Chao</creatorcontrib><creatorcontrib>Cheng Kangguo</creatorcontrib><creatorcontrib>Cai Xiuyu</creatorcontrib><creatorcontrib>Xie Ruilong</creatorcontrib><creatorcontrib>Koburger, III Charles William</creatorcontrib><creatorcontrib>Horak David Vaclav</creatorcontrib><creatorcontrib>Khakifirooz Ali</creatorcontrib><creatorcontrib>Ponoth Shom</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bergendahl Marc Adam</au><au>Standaert Theodorus Eduardus</au><au>Yang Chih-Chao</au><au>Cheng Kangguo</au><au>Cai Xiuyu</au><au>Xie Ruilong</au><au>Koburger, III Charles William</au><au>Horak David Vaclav</au><au>Khakifirooz Ali</au><au>Ponoth Shom</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Self-aligned dielectric isolation for FinFET devices</title><date>2017-04-18</date><risdate>2017</risdate><abstract>Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.</abstract><oa>free_for_read</oa></addata></record> |
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| title | Self-aligned dielectric isolation for FinFET devices |
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