Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints

The timing analysis of an integrated chip component using dynamic load sensitive timing feedback constraints maintaining the timing accuracy for all the boundary paths is achieved by capturing a reduced order representation for parasitic load within a component for each of its primary input and prim...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Ledalla Ravichander, Wood Michael H, Sinha Debjit, Bhanji Adil, Kalafala Kerim, Visweswariah Chandramouli
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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