Defect analysis assistance device, program executed by defect analysis assistance device, and defect analysis system
Conventionally, there was no method for automatically selecting the layers to be overlaid, so when the number of layers to be overlaid was large, there was a problem that much time was required for selecting the layers. It is an object of the present invention to provide a defect image analysis meth...
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| creator | Hirai Takehiro Obara Kenji Nakagaki Ryo |
| description | Conventionally, there was no method for automatically selecting the layers to be overlaid, so when the number of layers to be overlaid was large, there was a problem that much time was required for selecting the layers. It is an object of the present invention to provide a defect image analysis method capable of specifying patterns and layers in which a defect occurs by overlaying defect images to be analysis targets and design layout data, and a defect image analysis system capable of improving the efficiency to select the layers from the design layout data. The present invention is characterized in dividing analysis target images for each hierarchy corresponding to a manufacturing process and generating a plurality of layers; calculating a degree of matching between each of the layer division images and each design layer of the design layout data; and specifying a design layer with a highest degree of matching of the each design layer as a design layer corresponding to the layer division image. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9582875B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9582875B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9582875B23</originalsourceid><addsrcrecordid>eNrjZChxSU1LTS5RSMxLzKkszixWSCwGkiWJecmpCimpZZnJqToKBUX56UWJuQqpFanJpSWpKQpJlUA5gtoS81IwlBVXFpek5vIwsKYl5hSn8kJpbgYFN9cQZw_d1IL8-NTigsTk1LzUkvjQYEtTCyMLc1MnI2MilAAAHyBE6A</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Defect analysis assistance device, program executed by defect analysis assistance device, and defect analysis system</title><source>esp@cenet</source><creator>Hirai Takehiro ; Obara Kenji ; Nakagaki Ryo</creator><creatorcontrib>Hirai Takehiro ; Obara Kenji ; Nakagaki Ryo</creatorcontrib><description>Conventionally, there was no method for automatically selecting the layers to be overlaid, so when the number of layers to be overlaid was large, there was a problem that much time was required for selecting the layers. It is an object of the present invention to provide a defect image analysis method capable of specifying patterns and layers in which a defect occurs by overlaying defect images to be analysis targets and design layout data, and a defect image analysis system capable of improving the efficiency to select the layers from the design layout data. The present invention is characterized in dividing analysis target images for each hierarchy corresponding to a manufacturing process and generating a plurality of layers; calculating a degree of matching between each of the layer division images and each design layer of the design layout data; and specifying a design layer with a highest degree of matching of the each design layer as a design layer corresponding to the layer division image.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; HANDLING RECORD CARRIERS ; IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ; INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES ; MEASURING ; PHYSICS ; PRESENTATION OF DATA ; RECOGNITION OF DATA ; RECORD CARRIERS ; SEMICONDUCTOR DEVICES ; TESTING</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170228&DB=EPODOC&CC=US&NR=9582875B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170228&DB=EPODOC&CC=US&NR=9582875B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Hirai Takehiro</creatorcontrib><creatorcontrib>Obara Kenji</creatorcontrib><creatorcontrib>Nakagaki Ryo</creatorcontrib><title>Defect analysis assistance device, program executed by defect analysis assistance device, and defect analysis system</title><description>Conventionally, there was no method for automatically selecting the layers to be overlaid, so when the number of layers to be overlaid was large, there was a problem that much time was required for selecting the layers. It is an object of the present invention to provide a defect image analysis method capable of specifying patterns and layers in which a defect occurs by overlaying defect images to be analysis targets and design layout data, and a defect image analysis system capable of improving the efficiency to select the layers from the design layout data. The present invention is characterized in dividing analysis target images for each hierarchy corresponding to a manufacturing process and generating a plurality of layers; calculating a degree of matching between each of the layer division images and each design layer of the design layout data; and specifying a design layer with a highest degree of matching of the each design layer as a design layer corresponding to the layer division image.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>HANDLING RECORD CARRIERS</subject><subject>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</subject><subject>INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES</subject><subject>MEASURING</subject><subject>PHYSICS</subject><subject>PRESENTATION OF DATA</subject><subject>RECOGNITION OF DATA</subject><subject>RECORD CARRIERS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZChxSU1LTS5RSMxLzKkszixWSCwGkiWJecmpCimpZZnJqToKBUX56UWJuQqpFanJpSWpKQpJlUA5gtoS81IwlBVXFpek5vIwsKYl5hSn8kJpbgYFN9cQZw_d1IL8-NTigsTk1LzUkvjQYEtTCyMLc1MnI2MilAAAHyBE6A</recordid><startdate>20170228</startdate><enddate>20170228</enddate><creator>Hirai Takehiro</creator><creator>Obara Kenji</creator><creator>Nakagaki Ryo</creator><scope>EVB</scope></search><sort><creationdate>20170228</creationdate><title>Defect analysis assistance device, program executed by defect analysis assistance device, and defect analysis system</title><author>Hirai Takehiro ; Obara Kenji ; Nakagaki Ryo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9582875B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>HANDLING RECORD CARRIERS</topic><topic>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</topic><topic>INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES</topic><topic>MEASURING</topic><topic>PHYSICS</topic><topic>PRESENTATION OF DATA</topic><topic>RECOGNITION OF DATA</topic><topic>RECORD CARRIERS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>Hirai Takehiro</creatorcontrib><creatorcontrib>Obara Kenji</creatorcontrib><creatorcontrib>Nakagaki Ryo</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hirai Takehiro</au><au>Obara Kenji</au><au>Nakagaki Ryo</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Defect analysis assistance device, program executed by defect analysis assistance device, and defect analysis system</title><date>2017-02-28</date><risdate>2017</risdate><abstract>Conventionally, there was no method for automatically selecting the layers to be overlaid, so when the number of layers to be overlaid was large, there was a problem that much time was required for selecting the layers. It is an object of the present invention to provide a defect image analysis method capable of specifying patterns and layers in which a defect occurs by overlaying defect images to be analysis targets and design layout data, and a defect image analysis system capable of improving the efficiency to select the layers from the design layout data. The present invention is characterized in dividing analysis target images for each hierarchy corresponding to a manufacturing process and generating a plurality of layers; calculating a degree of matching between each of the layer division images and each design layer of the design layout data; and specifying a design layer with a highest degree of matching of the each design layer as a design layer corresponding to the layer division image.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY HANDLING RECORD CARRIERS IMAGE DATA PROCESSING OR GENERATION, IN GENERAL INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES MEASURING PHYSICS PRESENTATION OF DATA RECOGNITION OF DATA RECORD CARRIERS SEMICONDUCTOR DEVICES TESTING |
| title | Defect analysis assistance device, program executed by defect analysis assistance device, and defect analysis system |
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