Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same
A field effect transistor includes a body layer having a strained crystalline semiconductor channel region, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer that is lattice mismatched with the channel region, and a crystalline gate dielectric lay...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Rodder Mark S Bowen Robert C Obradovic Borna J |
| description | A field effect transistor includes a body layer having a strained crystalline semiconductor channel region, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer that is lattice mismatched with the channel region, and a crystalline gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9570609B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9570609B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9570609B23</originalsourceid><addsrcrecordid>eNqNizEKwkAQRdNYiHqHuUAgKCppDYq9CnZhTH6yC7uzYWcsvL0KHsDqFe-9eXFv8kuNQ_ACis9gfgoohSWpA4zUMn9UT51jEQQ6Ha9KLD1FmEu9Uhpo4Ef2HZuXkcyBlCOWxWzgoFj9uCi-a3MuMaUWOnEHgbW3S73dV7uqPqw3fyRvU7M6Iw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same</title><source>esp@cenet</source><creator>Rodder Mark S ; Bowen Robert C ; Obradovic Borna J</creator><creatorcontrib>Rodder Mark S ; Bowen Robert C ; Obradovic Borna J</creatorcontrib><description>A field effect transistor includes a body layer having a strained crystalline semiconductor channel region, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer that is lattice mismatched with the channel region, and a crystalline gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES ; NANOTECHNOLOGY ; PERFORMING OPERATIONS ; SEMICONDUCTOR DEVICES ; SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES ; TRANSPORTING</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170214&DB=EPODOC&CC=US&NR=9570609B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170214&DB=EPODOC&CC=US&NR=9570609B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Rodder Mark S</creatorcontrib><creatorcontrib>Bowen Robert C</creatorcontrib><creatorcontrib>Obradovic Borna J</creatorcontrib><title>Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same</title><description>A field effect transistor includes a body layer having a strained crystalline semiconductor channel region, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer that is lattice mismatched with the channel region, and a crystalline gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OR TREATMENT OF NANOSTRUCTURES</subject><subject>MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES</subject><subject>NANOTECHNOLOGY</subject><subject>PERFORMING OPERATIONS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES</subject><subject>TRANSPORTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNizEKwkAQRdNYiHqHuUAgKCppDYq9CnZhTH6yC7uzYWcsvL0KHsDqFe-9eXFv8kuNQ_ACis9gfgoohSWpA4zUMn9UT51jEQQ6Ha9KLD1FmEu9Uhpo4Ef2HZuXkcyBlCOWxWzgoFj9uCi-a3MuMaUWOnEHgbW3S73dV7uqPqw3fyRvU7M6Iw</recordid><startdate>20170214</startdate><enddate>20170214</enddate><creator>Rodder Mark S</creator><creator>Bowen Robert C</creator><creator>Obradovic Borna J</creator><scope>EVB</scope></search><sort><creationdate>20170214</creationdate><title>Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same</title><author>Rodder Mark S ; Bowen Robert C ; Obradovic Borna J</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9570609B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OR TREATMENT OF NANOSTRUCTURES</topic><topic>MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES</topic><topic>NANOTECHNOLOGY</topic><topic>PERFORMING OPERATIONS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES</topic><topic>TRANSPORTING</topic><toplevel>online_resources</toplevel><creatorcontrib>Rodder Mark S</creatorcontrib><creatorcontrib>Bowen Robert C</creatorcontrib><creatorcontrib>Obradovic Borna J</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Rodder Mark S</au><au>Bowen Robert C</au><au>Obradovic Borna J</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same</title><date>2017-02-14</date><risdate>2017</risdate><abstract>A field effect transistor includes a body layer having a strained crystalline semiconductor channel region, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer that is lattice mismatched with the channel region, and a crystalline gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US9570609B2 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OR TREATMENT OF NANOSTRUCTURES MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES NANOTECHNOLOGY PERFORMING OPERATIONS SEMICONDUCTOR DEVICES SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES TRANSPORTING |
| title | Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-10T07%3A13%3A53IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Rodder%20Mark%20S&rft.date=2017-02-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9570609B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |