Method of forming a self-aligned stack gate structure for use in a non-volatile memory array

A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second d...

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Hauptverfasser: Guyot Florence, Wege Stephan, Miridi Nadia, Do Nhan, Metzger-Brueckl Gerhard, Liu Xian, Om'mani Henry, Tadayoni Mandana, Toren Willem-Jan, Su Chieng-Sheng, Bernardi Cecile, Chen Yueh-Hsin, Cuevas Liz
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creator Guyot Florence
Wege Stephan
Miridi Nadia
Do Nhan
Metzger-Brueckl Gerhard
Liu Xian
Om'mani Henry
Tadayoni Mandana
Toren Willem-Jan
Su Chieng-Sheng
Bernardi Cecile
Chen Yueh-Hsin
Cuevas Liz
description A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9570581B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9570581B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9570581B23</originalsourceid><addsrcrecordid>eNqNyr0KwjAUhuEuDqLew7mBgD8U7aooLk7qJpRD-iUG05ySpELv3gpegNP7Ds-0eFyQn9KQGDISWxcsMSV4o9g7G9BQyqxfZDlj3Njr3Ed8LfUJ5MLIgwT1Fs_ZeVCLVuJAHCMP82Ji2Ccsfp0VdDreDmeFTmqkjjUCcn2_VuV2We5W-_XmD_IB6IE7Ew</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of forming a self-aligned stack gate structure for use in a non-volatile memory array</title><source>esp@cenet</source><creator>Guyot Florence ; Wege Stephan ; Miridi Nadia ; Do Nhan ; Metzger-Brueckl Gerhard ; Liu Xian ; Om'mani Henry ; Tadayoni Mandana ; Toren Willem-Jan ; Su Chieng-Sheng ; Bernardi Cecile ; Chen Yueh-Hsin ; Cuevas Liz</creator><creatorcontrib>Guyot Florence ; Wege Stephan ; Miridi Nadia ; Do Nhan ; Metzger-Brueckl Gerhard ; Liu Xian ; Om'mani Henry ; Tadayoni Mandana ; Toren Willem-Jan ; Su Chieng-Sheng ; Bernardi Cecile ; Chen Yueh-Hsin ; Cuevas Liz</creatorcontrib><description>A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170214&amp;DB=EPODOC&amp;CC=US&amp;NR=9570581B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25568,76551</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170214&amp;DB=EPODOC&amp;CC=US&amp;NR=9570581B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Guyot Florence</creatorcontrib><creatorcontrib>Wege Stephan</creatorcontrib><creatorcontrib>Miridi Nadia</creatorcontrib><creatorcontrib>Do Nhan</creatorcontrib><creatorcontrib>Metzger-Brueckl Gerhard</creatorcontrib><creatorcontrib>Liu Xian</creatorcontrib><creatorcontrib>Om'mani Henry</creatorcontrib><creatorcontrib>Tadayoni Mandana</creatorcontrib><creatorcontrib>Toren Willem-Jan</creatorcontrib><creatorcontrib>Su Chieng-Sheng</creatorcontrib><creatorcontrib>Bernardi Cecile</creatorcontrib><creatorcontrib>Chen Yueh-Hsin</creatorcontrib><creatorcontrib>Cuevas Liz</creatorcontrib><title>Method of forming a self-aligned stack gate structure for use in a non-volatile memory array</title><description>A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyr0KwjAUhuEuDqLew7mBgD8U7aooLk7qJpRD-iUG05ySpELv3gpegNP7Ds-0eFyQn9KQGDISWxcsMSV4o9g7G9BQyqxfZDlj3Njr3Ed8LfUJ5MLIgwT1Fs_ZeVCLVuJAHCMP82Ji2Ccsfp0VdDreDmeFTmqkjjUCcn2_VuV2We5W-_XmD_IB6IE7Ew</recordid><startdate>20170214</startdate><enddate>20170214</enddate><creator>Guyot Florence</creator><creator>Wege Stephan</creator><creator>Miridi Nadia</creator><creator>Do Nhan</creator><creator>Metzger-Brueckl Gerhard</creator><creator>Liu Xian</creator><creator>Om'mani Henry</creator><creator>Tadayoni Mandana</creator><creator>Toren Willem-Jan</creator><creator>Su Chieng-Sheng</creator><creator>Bernardi Cecile</creator><creator>Chen Yueh-Hsin</creator><creator>Cuevas Liz</creator><scope>EVB</scope></search><sort><creationdate>20170214</creationdate><title>Method of forming a self-aligned stack gate structure for use in a non-volatile memory array</title><author>Guyot Florence ; Wege Stephan ; Miridi Nadia ; Do Nhan ; Metzger-Brueckl Gerhard ; Liu Xian ; Om'mani Henry ; Tadayoni Mandana ; Toren Willem-Jan ; Su Chieng-Sheng ; Bernardi Cecile ; Chen Yueh-Hsin ; Cuevas Liz</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9570581B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Guyot Florence</creatorcontrib><creatorcontrib>Wege Stephan</creatorcontrib><creatorcontrib>Miridi Nadia</creatorcontrib><creatorcontrib>Do Nhan</creatorcontrib><creatorcontrib>Metzger-Brueckl Gerhard</creatorcontrib><creatorcontrib>Liu Xian</creatorcontrib><creatorcontrib>Om'mani Henry</creatorcontrib><creatorcontrib>Tadayoni Mandana</creatorcontrib><creatorcontrib>Toren Willem-Jan</creatorcontrib><creatorcontrib>Su Chieng-Sheng</creatorcontrib><creatorcontrib>Bernardi Cecile</creatorcontrib><creatorcontrib>Chen Yueh-Hsin</creatorcontrib><creatorcontrib>Cuevas Liz</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Guyot Florence</au><au>Wege Stephan</au><au>Miridi Nadia</au><au>Do Nhan</au><au>Metzger-Brueckl Gerhard</au><au>Liu Xian</au><au>Om'mani Henry</au><au>Tadayoni Mandana</au><au>Toren Willem-Jan</au><au>Su Chieng-Sheng</au><au>Bernardi Cecile</au><au>Chen Yueh-Hsin</au><au>Cuevas Liz</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of forming a self-aligned stack gate structure for use in a non-volatile memory array</title><date>2017-02-14</date><risdate>2017</risdate><abstract>A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Method of forming a self-aligned stack gate structure for use in a non-volatile memory array
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-17T00%3A36%3A33IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Guyot%20Florence&rft.date=2017-02-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9570581B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true