Microelectronic interconnect element with decreased conductor spacing
A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces abov...
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creator | Ryu Chang Myung Endo Kimitaka Haba Belgacem Kubota Yoichi |
description | A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9524947B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9524947B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9524947B23</originalsourceid><addsrcrecordid>eNrjZHD1zUwuyk_NSU0uKcrPy0xWyMwrSS1Kzs_LA4ooAMVzU_NKFMozSzIUUlKTi1ITi1NTFIDSKaXJJflFCsUFicmZeek8DKxpiTnFqbxQmptBwc01xNlDN7UgPz4VpCg1L7UkPjTY0tTIxNLE3MnImAglAAsTM_g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Microelectronic interconnect element with decreased conductor spacing</title><source>esp@cenet</source><creator>Ryu Chang Myung ; Endo Kimitaka ; Haba Belgacem ; Kubota Yoichi</creator><creatorcontrib>Ryu Chang Myung ; Endo Kimitaka ; Haba Belgacem ; Kubota Yoichi</creatorcontrib><description>A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.</description><language>eng</language><subject>APPARATUS THEREFOR ; BASIC ELECTRIC ELEMENTS ; CHEMISTRY ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; ELECTROFORMING ; ELECTROLYTIC OR ELECTROPHORETIC PROCESSES ; METALLURGY ; MICROSTRUCTURAL TECHNOLOGY ; PERFORMING OPERATIONS ; PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTIONOF COATINGS ; PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS ; SEMICONDUCTOR DEVICES ; TRANSPORTING</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20161220&DB=EPODOC&CC=US&NR=9524947B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25555,76308</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20161220&DB=EPODOC&CC=US&NR=9524947B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ryu Chang Myung</creatorcontrib><creatorcontrib>Endo Kimitaka</creatorcontrib><creatorcontrib>Haba Belgacem</creatorcontrib><creatorcontrib>Kubota Yoichi</creatorcontrib><title>Microelectronic interconnect element with decreased conductor spacing</title><description>A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.</description><subject>APPARATUS THEREFOR</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CHEMISTRY</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>ELECTROFORMING</subject><subject>ELECTROLYTIC OR ELECTROPHORETIC PROCESSES</subject><subject>METALLURGY</subject><subject>MICROSTRUCTURAL TECHNOLOGY</subject><subject>PERFORMING OPERATIONS</subject><subject>PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTIONOF COATINGS</subject><subject>PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TRANSPORTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHD1zUwuyk_NSU0uKcrPy0xWyMwrSS1Kzs_LA4ooAMVzU_NKFMozSzIUUlKTi1ITi1NTFIDSKaXJJflFCsUFicmZeek8DKxpiTnFqbxQmptBwc01xNlDN7UgPz4VpCg1L7UkPjTY0tTIxNLE3MnImAglAAsTM_g</recordid><startdate>20161220</startdate><enddate>20161220</enddate><creator>Ryu Chang Myung</creator><creator>Endo Kimitaka</creator><creator>Haba Belgacem</creator><creator>Kubota Yoichi</creator><scope>EVB</scope></search><sort><creationdate>20161220</creationdate><title>Microelectronic interconnect element with decreased conductor spacing</title><author>Ryu Chang Myung ; Endo Kimitaka ; Haba Belgacem ; Kubota Yoichi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9524947B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>APPARATUS THEREFOR</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CHEMISTRY</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>ELECTROFORMING</topic><topic>ELECTROLYTIC OR ELECTROPHORETIC PROCESSES</topic><topic>METALLURGY</topic><topic>MICROSTRUCTURAL TECHNOLOGY</topic><topic>PERFORMING OPERATIONS</topic><topic>PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTIONOF COATINGS</topic><topic>PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TRANSPORTING</topic><toplevel>online_resources</toplevel><creatorcontrib>Ryu Chang Myung</creatorcontrib><creatorcontrib>Endo Kimitaka</creatorcontrib><creatorcontrib>Haba Belgacem</creatorcontrib><creatorcontrib>Kubota Yoichi</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ryu Chang Myung</au><au>Endo Kimitaka</au><au>Haba Belgacem</au><au>Kubota Yoichi</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Microelectronic interconnect element with decreased conductor spacing</title><date>2016-12-20</date><risdate>2016</risdate><abstract>A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | APPARATUS THEREFOR BASIC ELECTRIC ELEMENTS CHEMISTRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY ELECTROFORMING ELECTROLYTIC OR ELECTROPHORETIC PROCESSES METALLURGY MICROSTRUCTURAL TECHNOLOGY PERFORMING OPERATIONS PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTIONOF COATINGS PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS SEMICONDUCTOR DEVICES TRANSPORTING |
title | Microelectronic interconnect element with decreased conductor spacing |
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