Programmable delay circuit for low power applications

Programmable delay circuits are described herein according to embodiments of the present disclosure. In one embodiment, a delay circuit comprises a plurality of delay stages coupled in series. Each of the delay stages comprises a delay gate on a forward path of the delay circuit, wherein the delay g...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Sridhar Shraddha, Diffenderfer Jan Christian, Singh Guneet, Fertsch Michael Thomas
Format: Patent
Sprache:eng
Schlagworte:
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