Self-stop gate recess etching process for semiconductor field effect transistors

A field effect transistor (FET) device including a GaAs substrate, an AlGaAs buffer layer provided on the substrate, an InGaAs channel layer provided on the buffer layer, an AlGaAs barrier layer provided on the channel layer, a GaAs undoped etch stop layer provided on the barrier layer where the undoped layer defines a depth of a gate recess in the FET device, and a heavily doped GaAs cap layer provided on the etch stop layer. The cap layer has a predetermined thickness and the thickness of the combination of the barrier layer and the undoped layer has the predetermined thickness, where the thickness of the undoped layer and the thickness of the barrier layer are selectively provided relative to each other so as to define the depth of the gate recess.