Combined rank and linear address incrementing utility for computer memory test operations

Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the ad...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Wellwood George C, Meaney Patrick J, Curley Lawrence D
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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