Write address synchronization in 2 read/1write SRAM arrays

An aspect relates to a memory array that includes at least a first and a second six transistor static random access memory cell, and first and second address decoders. The first address decoder comprises a first latch, the second address decoder a second latch. First and second address data paths pr...

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Bibliographische Detailangaben

Hauptverfasser:	Barowski Harry, Penth Silke, Penth Wolfgang, Werner Tobias
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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