ECC bypass using low latency CE correction with retry select signal

A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and,...

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Bibliographische Detailangaben

Hauptverfasser:	Goodman Benjiman L, Retter Eric E, Lastras-Montano Luis A, Wright Kenneth L
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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