Phase shifted coarse/fine clock dithering responsive to controller select signals

A clock dithering circuit that provides cancellation of digital noise spurs is disclosed. The clock dithering circuit includes a control unit that receives an input clock. An ICG (integrated clock gating) cell receives the input clock and receives an enable signal from the control unit. The ICG cell generates a gated clock. A coarse dither unit receives the gated clock and receives a coarse select signal from the control unit. The coarse dither unit generates a coarse dither clock. A fine dither unit receives the coarse dither clock and receives a fine select signal from the control unit. The fine dither unit generates a fine dither clock.