Semiconductor wafer and method of fabricating an IC die

There is provided a semiconductor wafer comprising a plurality of replicated IC modules. Each replicated IC module is capable of forming an individual IC die. The semiconductor wafer further comprises inter-module cross-wafer electrical connections, and the replicated IC modules are further arranged...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Maiolani Mark, Moran Robert F, Beattie Derek
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Maiolani Mark
Moran Robert F
Beattie Derek
description There is provided a semiconductor wafer comprising a plurality of replicated IC modules. Each replicated IC module is capable of forming an individual IC die. The semiconductor wafer further comprises inter-module cross-wafer electrical connections, and the replicated IC modules are further arranged to be cut into IC dies comprising multiple replicated IC modules. There is further provided a method of fabricating an IC die. The method comprises fabricating such a semiconductor wafer, determining a required configuration of replicated IC modules, identifying inter-module boundaries along which to cut the semiconductor wafer to achieve the required configuration of replicated IC modules, and cutting the semiconductor wafer along the identified inter-module boundaries to produce at least one IC die comprising the required configuration of replicated IC modules.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9406347B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9406347B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9406347B23</originalsourceid><addsrcrecordid>eNrjZDAPTs3NTM7PSylNLskvUihPTEstUkjMS1HITS3JyE9RyE9TSEtMKspMTizJzEsHyih4OiukZKbyMLCmJeYUp_JCaW4GBTfXEGcP3dSC_PjU4oLE5NS81JL40GBLEwMzYxNzJyNjIpQAAD5ALPY</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor wafer and method of fabricating an IC die</title><source>esp@cenet</source><creator>Maiolani Mark ; Moran Robert F ; Beattie Derek</creator><creatorcontrib>Maiolani Mark ; Moran Robert F ; Beattie Derek</creatorcontrib><description>There is provided a semiconductor wafer comprising a plurality of replicated IC modules. Each replicated IC module is capable of forming an individual IC die. The semiconductor wafer further comprises inter-module cross-wafer electrical connections, and the replicated IC modules are further arranged to be cut into IC dies comprising multiple replicated IC modules. There is further provided a method of fabricating an IC die. The method comprises fabricating such a semiconductor wafer, determining a required configuration of replicated IC modules, identifying inter-module boundaries along which to cut the semiconductor wafer to achieve the required configuration of replicated IC modules, and cutting the semiconductor wafer along the identified inter-module boundaries to produce at least one IC die comprising the required configuration of replicated IC modules.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160802&amp;DB=EPODOC&amp;CC=US&amp;NR=9406347B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160802&amp;DB=EPODOC&amp;CC=US&amp;NR=9406347B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Maiolani Mark</creatorcontrib><creatorcontrib>Moran Robert F</creatorcontrib><creatorcontrib>Beattie Derek</creatorcontrib><title>Semiconductor wafer and method of fabricating an IC die</title><description>There is provided a semiconductor wafer comprising a plurality of replicated IC modules. Each replicated IC module is capable of forming an individual IC die. The semiconductor wafer further comprises inter-module cross-wafer electrical connections, and the replicated IC modules are further arranged to be cut into IC dies comprising multiple replicated IC modules. There is further provided a method of fabricating an IC die. The method comprises fabricating such a semiconductor wafer, determining a required configuration of replicated IC modules, identifying inter-module boundaries along which to cut the semiconductor wafer to achieve the required configuration of replicated IC modules, and cutting the semiconductor wafer along the identified inter-module boundaries to produce at least one IC die comprising the required configuration of replicated IC modules.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAPTs3NTM7PSylNLskvUihPTEstUkjMS1HITS3JyE9RyE9TSEtMKspMTizJzEsHyih4OiukZKbyMLCmJeYUp_JCaW4GBTfXEGcP3dSC_PjU4oLE5NS81JL40GBLEwMzYxNzJyNjIpQAAD5ALPY</recordid><startdate>20160802</startdate><enddate>20160802</enddate><creator>Maiolani Mark</creator><creator>Moran Robert F</creator><creator>Beattie Derek</creator><scope>EVB</scope></search><sort><creationdate>20160802</creationdate><title>Semiconductor wafer and method of fabricating an IC die</title><author>Maiolani Mark ; Moran Robert F ; Beattie Derek</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9406347B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Maiolani Mark</creatorcontrib><creatorcontrib>Moran Robert F</creatorcontrib><creatorcontrib>Beattie Derek</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Maiolani Mark</au><au>Moran Robert F</au><au>Beattie Derek</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor wafer and method of fabricating an IC die</title><date>2016-08-02</date><risdate>2016</risdate><abstract>There is provided a semiconductor wafer comprising a plurality of replicated IC modules. Each replicated IC module is capable of forming an individual IC die. The semiconductor wafer further comprises inter-module cross-wafer electrical connections, and the replicated IC modules are further arranged to be cut into IC dies comprising multiple replicated IC modules. There is further provided a method of fabricating an IC die. The method comprises fabricating such a semiconductor wafer, determining a required configuration of replicated IC modules, identifying inter-module boundaries along which to cut the semiconductor wafer to achieve the required configuration of replicated IC modules, and cutting the semiconductor wafer along the identified inter-module boundaries to produce at least one IC die comprising the required configuration of replicated IC modules.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US9406347B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
title Semiconductor wafer and method of fabricating an IC die
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-06T06%3A03%3A11IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Maiolani%20Mark&rft.date=2016-08-02&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9406347B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true