Configurable delay circuit and method of clock buffering

An SRAM clock circuit and an SRAM. In one embodiment, the SRAM clock circuit includes: (1) a plurality of transistor stacks optionally serially electrically couplable to form a configurable delay path through which a clock signal is buffered, and (2) a delay path select circuit respectively electric...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	WANG LEI, JIANG ZHENYE, LIN HWONG-KWO, GOLD SPENCER
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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