Anti-tamper system based on dual random bits generators for integrated circuits
An apparatus includes a mesh block, a first number generator configured to generate a first number, a second number generator configured to generate a second number, and a comparator block configured to compare the first number with the second number and generate an output signal from the mesh block...
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| creator | A/L KRISHNASAMY RAJ KUMAR THUM CHIA CHIEH LEE MOO KIT |
| description | An apparatus includes a mesh block, a first number generator configured to generate a first number, a second number generator configured to generate a second number, and a comparator block configured to compare the first number with the second number and generate an output signal from the mesh block. The output signal indicates an occurrence of an unauthorized activity on the mesh block. |
| format | Patent |
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| subjects | ADVERTISING CALCULATING CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS CODING OR CIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHERPURPOSES INVOLVING THE NEED FOR SECRECY COMPUTING COUNTING CRYPTOGRAPHY DISPLAY EDUCATION ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PHYSICS PRINTED CIRCUITS SEALS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
| title | Anti-tamper system based on dual random bits generators for integrated circuits |
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