Hierarchical, distributed built-in self-repair solution
A built-in self-test (BIST) circuit to test one or more memory blocks on an integrated circuit. The one or more memory blocks further includes a first memory block and a second memory block A built-in soft-repair controller (BISoR) is provided to soft repair the one or more memory blocks. The BIST c...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | ELLUR HARSHARAJ VARADARAJAN DEVANATHAN KS RAGHAVENDRA PRASAD |
description | A built-in self-test (BIST) circuit to test one or more memory blocks on an integrated circuit. The one or more memory blocks further includes a first memory block and a second memory block A built-in soft-repair controller (BISoR) is provided to soft repair the one or more memory blocks. The BIST circuit in conjunction with the BISoR is configured to test and soft repair the first memory block before performing test and soft repair of the second memory block. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9318222B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9318222B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9318222B23</originalsourceid><addsrcrecordid>eNrjZDD3yEwtSixKzshMTszRUUjJLC4pykwqLUlNUUgqzcwp0c3MUyhOzUnTLUotSMwsUijOzyktyczP42FgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHBlsaGFkZGRk5GxkQoAQCWyi3v</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Hierarchical, distributed built-in self-repair solution</title><source>esp@cenet</source><creator>ELLUR HARSHARAJ ; VARADARAJAN DEVANATHAN ; KS RAGHAVENDRA PRASAD</creator><creatorcontrib>ELLUR HARSHARAJ ; VARADARAJAN DEVANATHAN ; KS RAGHAVENDRA PRASAD</creatorcontrib><description>A built-in self-test (BIST) circuit to test one or more memory blocks on an integrated circuit. The one or more memory blocks further includes a first memory block and a second memory block A built-in soft-repair controller (BISoR) is provided to soft repair the one or more memory blocks. The BIST circuit in conjunction with the BISoR is configured to test and soft repair the first memory block before performing test and soft repair of the second memory block.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160419&DB=EPODOC&CC=US&NR=9318222B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160419&DB=EPODOC&CC=US&NR=9318222B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ELLUR HARSHARAJ</creatorcontrib><creatorcontrib>VARADARAJAN DEVANATHAN</creatorcontrib><creatorcontrib>KS RAGHAVENDRA PRASAD</creatorcontrib><title>Hierarchical, distributed built-in self-repair solution</title><description>A built-in self-test (BIST) circuit to test one or more memory blocks on an integrated circuit. The one or more memory blocks further includes a first memory block and a second memory block A built-in soft-repair controller (BISoR) is provided to soft repair the one or more memory blocks. The BIST circuit in conjunction with the BISoR is configured to test and soft repair the first memory block before performing test and soft repair of the second memory block.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD3yEwtSixKzshMTszRUUjJLC4pykwqLUlNUUgqzcwp0c3MUyhOzUnTLUotSMwsUijOzyktyczP42FgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHBlsaGFkZGRk5GxkQoAQCWyi3v</recordid><startdate>20160419</startdate><enddate>20160419</enddate><creator>ELLUR HARSHARAJ</creator><creator>VARADARAJAN DEVANATHAN</creator><creator>KS RAGHAVENDRA PRASAD</creator><scope>EVB</scope></search><sort><creationdate>20160419</creationdate><title>Hierarchical, distributed built-in self-repair solution</title><author>ELLUR HARSHARAJ ; VARADARAJAN DEVANATHAN ; KS RAGHAVENDRA PRASAD</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9318222B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>ELLUR HARSHARAJ</creatorcontrib><creatorcontrib>VARADARAJAN DEVANATHAN</creatorcontrib><creatorcontrib>KS RAGHAVENDRA PRASAD</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ELLUR HARSHARAJ</au><au>VARADARAJAN DEVANATHAN</au><au>KS RAGHAVENDRA PRASAD</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Hierarchical, distributed built-in self-repair solution</title><date>2016-04-19</date><risdate>2016</risdate><abstract>A built-in self-test (BIST) circuit to test one or more memory blocks on an integrated circuit. The one or more memory blocks further includes a first memory block and a second memory block A built-in soft-repair controller (BISoR) is provided to soft repair the one or more memory blocks. The BIST circuit in conjunction with the BISoR is configured to test and soft repair the first memory block before performing test and soft repair of the second memory block.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US9318222B2 |
source | esp@cenet |
subjects | INFORMATION STORAGE PHYSICS STATIC STORES |
title | Hierarchical, distributed built-in self-repair solution |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-13T00%3A54%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=ELLUR%20HARSHARAJ&rft.date=2016-04-19&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9318222B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |