Configurable voltage reduction for register file

A system, a memory device and a method are contemplated in which the apparatus may include a plurality of memory cells, a plurality of voltage reduction circuits, and control circuitry. The plurality of voltage reduction circuits may be configured to reduce a voltage level of a power supply coupled...

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Bibliographische Detailangaben

Hauptverfasser:	BHATIA AJAY KUMAR, MEHTA ANSHUL Y, HESS GREG M, BARN AMRINDER S
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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