Integrated circuits with separate workfunction material layers and methods for fabricating the same
Integrated circuits employing replacement metal gate technologies with separate workfunction material layers and raised source/drain structures and methods for fabricating the same are disclosed herein. In one exemplary embodiment, a method of fabricating an integrated circuit includes forming a fir...
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| creator | JAKUBOWSKI FRANK FAUL JUERGEN |
| description | Integrated circuits employing replacement metal gate technologies with separate workfunction material layers and raised source/drain structures and methods for fabricating the same are disclosed herein. In one exemplary embodiment, a method of fabricating an integrated circuit includes forming a first workfunction material layer over an ILD layer, along the sidewall spacer structures, and over the high-k material layer. The method further includes forming a masking layer over the first workfunction material layer, performing a tilted ion implant wherein ions are implanted at the masking layer over the ILD layer and along the sidewall spacer structures, selectively etching the masking layer and the first workfunction material from over the ILD layer and from along the sidewall spacer structures, and forming a second workfunction material layer over the ILD layer, along the sidewall spacer structures, and over the first workfunction material layer. |
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In one exemplary embodiment, a method of fabricating an integrated circuit includes forming a first workfunction material layer over an ILD layer, along the sidewall spacer structures, and over the high-k material layer. The method further includes forming a masking layer over the first workfunction material layer, performing a tilted ion implant wherein ions are implanted at the masking layer over the ILD layer and along the sidewall spacer structures, selectively etching the masking layer and the first workfunction material from over the ILD layer and from along the sidewall spacer structures, and forming a second workfunction material layer over the ILD layer, along the sidewall spacer structures, and over the first workfunction material layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160329&DB=EPODOC&CC=US&NR=9299616B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160329&DB=EPODOC&CC=US&NR=9299616B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JAKUBOWSKI FRANK</creatorcontrib><creatorcontrib>FAUL JUERGEN</creatorcontrib><title>Integrated circuits with separate workfunction material layers and methods for fabricating the same</title><description>Integrated circuits employing replacement metal gate technologies with separate workfunction material layers and raised source/drain structures and methods for fabricating the same are disclosed herein. In one exemplary embodiment, a method of fabricating an integrated circuit includes forming a first workfunction material layer over an ILD layer, along the sidewall spacer structures, and over the high-k material layer. The method further includes forming a masking layer over the first workfunction material layer, performing a tilted ion implant wherein ions are implanted at the masking layer over the ILD layer and along the sidewall spacer structures, selectively etching the masking layer and the first workfunction material from over the ILD layer and from along the sidewall spacer structures, and forming a second workfunction material layer over the ILD layer, along the sidewall spacer structures, and over the first workfunction material layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNykEKwkAMQNFuXIh6h1zARRUK3SqKrtV1iTOZNnQ6U5KU4u1V8ACuPjz-snDXZNQKGnlwLG5iU5jZOlAa8eswZ-nDlJxxTjB8RBgjRHyRKGDyMJB12SuELBDwKezQOLVgHYHiQOtiETAqbX5dFXA-3Y-XLY25IR3RUSJrHrd6V9dVWR3K_R_LG5rnPwM</recordid><startdate>20160329</startdate><enddate>20160329</enddate><creator>JAKUBOWSKI FRANK</creator><creator>FAUL JUERGEN</creator><scope>EVB</scope></search><sort><creationdate>20160329</creationdate><title>Integrated circuits with separate workfunction material layers and methods for fabricating the same</title><author>JAKUBOWSKI FRANK ; FAUL JUERGEN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9299616B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>JAKUBOWSKI FRANK</creatorcontrib><creatorcontrib>FAUL JUERGEN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JAKUBOWSKI FRANK</au><au>FAUL JUERGEN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuits with separate workfunction material layers and methods for fabricating the same</title><date>2016-03-29</date><risdate>2016</risdate><abstract>Integrated circuits employing replacement metal gate technologies with separate workfunction material layers and raised source/drain structures and methods for fabricating the same are disclosed herein. In one exemplary embodiment, a method of fabricating an integrated circuit includes forming a first workfunction material layer over an ILD layer, along the sidewall spacer structures, and over the high-k material layer. The method further includes forming a masking layer over the first workfunction material layer, performing a tilted ion implant wherein ions are implanted at the masking layer over the ILD layer and along the sidewall spacer structures, selectively etching the masking layer and the first workfunction material from over the ILD layer and from along the sidewall spacer structures, and forming a second workfunction material layer over the ILD layer, along the sidewall spacer structures, and over the first workfunction material layer.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Integrated circuits with separate workfunction material layers and methods for fabricating the same |
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