Integrated circuit packaging system with planarity control and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a partially removed portion including: a conductive pattern having a lower surface on a top frame surface of the leadframe, a contact protrusion and a support lead on the lower surface of the con...
Gespeichert in:
Hauptverfasser: | , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | ESPIRITU EMMANUEL TRASPORTO ARNEL SENOSA DO BYUNG TAI CHUA LINDA PEI EE |
description | A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a partially removed portion including: a conductive pattern having a lower surface on a top frame surface of the leadframe, a contact protrusion and a support lead on the lower surface of the conductive pattern, the support lead for supporting the partially removed portion of the leadframe during an encapsulation process, and a contact pad on a bottom surface of the contact protrusion; mounting an integrated circuit die above the conductive pattern; applying an encapsulation on the integrated circuit die and the conductive pattern, the lower surface of the conductive pattern exposed from the encapsulation; and removing at least a portion of the leadframe to form a contact lead and expose a bottom surface of the encapsulation. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9293351B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9293351B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9293351B23</originalsourceid><addsrcrecordid>eNqNzT0KAjEQQOFtLES9w1zAwg0W2yqK1monLEN28oPJJCQTZG-vhQewes0Hb9k9ryxkCwpNoH3RzQtk1C-0ni3UuQpFeHtxkAMyFi8z6MRSUgDkCSKJSxMkAxG5GdTSCoE4KpTMulsYDJU2v646OJ_ux8uWchqpfj_EJOPjNvSDUvvdoVd_kA-mfjxb</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Integrated circuit packaging system with planarity control and method of manufacture thereof</title><source>esp@cenet</source><creator>ESPIRITU EMMANUEL ; TRASPORTO ARNEL SENOSA ; DO BYUNG TAI ; CHUA LINDA PEI EE</creator><creatorcontrib>ESPIRITU EMMANUEL ; TRASPORTO ARNEL SENOSA ; DO BYUNG TAI ; CHUA LINDA PEI EE</creatorcontrib><description>A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a partially removed portion including: a conductive pattern having a lower surface on a top frame surface of the leadframe, a contact protrusion and a support lead on the lower surface of the conductive pattern, the support lead for supporting the partially removed portion of the leadframe during an encapsulation process, and a contact pad on a bottom surface of the contact protrusion; mounting an integrated circuit die above the conductive pattern; applying an encapsulation on the integrated circuit die and the conductive pattern, the lower surface of the conductive pattern exposed from the encapsulation; and removing at least a portion of the leadframe to form a contact lead and expose a bottom surface of the encapsulation.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160322&DB=EPODOC&CC=US&NR=9293351B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160322&DB=EPODOC&CC=US&NR=9293351B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ESPIRITU EMMANUEL</creatorcontrib><creatorcontrib>TRASPORTO ARNEL SENOSA</creatorcontrib><creatorcontrib>DO BYUNG TAI</creatorcontrib><creatorcontrib>CHUA LINDA PEI EE</creatorcontrib><title>Integrated circuit packaging system with planarity control and method of manufacture thereof</title><description>A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a partially removed portion including: a conductive pattern having a lower surface on a top frame surface of the leadframe, a contact protrusion and a support lead on the lower surface of the conductive pattern, the support lead for supporting the partially removed portion of the leadframe during an encapsulation process, and a contact pad on a bottom surface of the contact protrusion; mounting an integrated circuit die above the conductive pattern; applying an encapsulation on the integrated circuit die and the conductive pattern, the lower surface of the conductive pattern exposed from the encapsulation; and removing at least a portion of the leadframe to form a contact lead and expose a bottom surface of the encapsulation.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNzT0KAjEQQOFtLES9w1zAwg0W2yqK1monLEN28oPJJCQTZG-vhQewes0Hb9k9ryxkCwpNoH3RzQtk1C-0ni3UuQpFeHtxkAMyFi8z6MRSUgDkCSKJSxMkAxG5GdTSCoE4KpTMulsYDJU2v646OJ_ux8uWchqpfj_EJOPjNvSDUvvdoVd_kA-mfjxb</recordid><startdate>20160322</startdate><enddate>20160322</enddate><creator>ESPIRITU EMMANUEL</creator><creator>TRASPORTO ARNEL SENOSA</creator><creator>DO BYUNG TAI</creator><creator>CHUA LINDA PEI EE</creator><scope>EVB</scope></search><sort><creationdate>20160322</creationdate><title>Integrated circuit packaging system with planarity control and method of manufacture thereof</title><author>ESPIRITU EMMANUEL ; TRASPORTO ARNEL SENOSA ; DO BYUNG TAI ; CHUA LINDA PEI EE</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9293351B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>ESPIRITU EMMANUEL</creatorcontrib><creatorcontrib>TRASPORTO ARNEL SENOSA</creatorcontrib><creatorcontrib>DO BYUNG TAI</creatorcontrib><creatorcontrib>CHUA LINDA PEI EE</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ESPIRITU EMMANUEL</au><au>TRASPORTO ARNEL SENOSA</au><au>DO BYUNG TAI</au><au>CHUA LINDA PEI EE</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit packaging system with planarity control and method of manufacture thereof</title><date>2016-03-22</date><risdate>2016</risdate><abstract>A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a partially removed portion including: a conductive pattern having a lower surface on a top frame surface of the leadframe, a contact protrusion and a support lead on the lower surface of the conductive pattern, the support lead for supporting the partially removed portion of the leadframe during an encapsulation process, and a contact pad on a bottom surface of the contact protrusion; mounting an integrated circuit die above the conductive pattern; applying an encapsulation on the integrated circuit die and the conductive pattern, the lower surface of the conductive pattern exposed from the encapsulation; and removing at least a portion of the leadframe to form a contact lead and expose a bottom surface of the encapsulation.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US9293351B2 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Integrated circuit packaging system with planarity control and method of manufacture thereof |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-19T18%3A53%3A15IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=ESPIRITU%20EMMANUEL&rft.date=2016-03-22&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9293351B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |