Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary
A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as...
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| creator | CHOU CHIENUN SWARBRICK IAN ANDREW VAKILOTOJAR VIDA HAMILTON STEPHEN W WINGARD DREW E |
| description | A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel. |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary |
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