Information processing device including memory management device managing access from processor to memory and memory management method
A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a fi...
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| creator | NOZUE HIROSHI SAKAMOTO HIROYUKI KAWAGOME KAZUHIRO MIYAGAWA MASAKI NAKAI HIROTO KUNIMATSU ATSUSHI MAEDA KENICHI |
| description | A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9280466B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9280466B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9280466B23</originalsourceid><addsrcrecordid>eNqNjDEKAjEQRdNYiHqHuYAgqyzaKorWar0Myewa2JkJSRS8gOeWiNtZWH14vPfH5nWSViNj9ioQolpKyUsHjh7eEnix_d0VwMQan8Ao2BGT5EH5kGKgLTG0UXl40ghZhxTF_Xhhyjd1UzNqsU80--7EwGF_2R3nFLShFNCSUG6u5021Xqzqelst_1DeZoFMiQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Information processing device including memory management device managing access from processor to memory and memory management method</title><source>esp@cenet</source><creator>NOZUE HIROSHI ; SAKAMOTO HIROYUKI ; KAWAGOME KAZUHIRO ; MIYAGAWA MASAKI ; NAKAI HIROTO ; KUNIMATSU ATSUSHI ; MAEDA KENICHI</creator><creatorcontrib>NOZUE HIROSHI ; SAKAMOTO HIROYUKI ; KAWAGOME KAZUHIRO ; MIYAGAWA MASAKI ; NAKAI HIROTO ; KUNIMATSU ATSUSHI ; MAEDA KENICHI</creatorcontrib><description>A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160308&DB=EPODOC&CC=US&NR=9280466B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160308&DB=EPODOC&CC=US&NR=9280466B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NOZUE HIROSHI</creatorcontrib><creatorcontrib>SAKAMOTO HIROYUKI</creatorcontrib><creatorcontrib>KAWAGOME KAZUHIRO</creatorcontrib><creatorcontrib>MIYAGAWA MASAKI</creatorcontrib><creatorcontrib>NAKAI HIROTO</creatorcontrib><creatorcontrib>KUNIMATSU ATSUSHI</creatorcontrib><creatorcontrib>MAEDA KENICHI</creatorcontrib><title>Information processing device including memory management device managing access from processor to memory and memory management method</title><description>A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjDEKAjEQRdNYiHqHuYAgqyzaKorWar0Myewa2JkJSRS8gOeWiNtZWH14vPfH5nWSViNj9ioQolpKyUsHjh7eEnix_d0VwMQan8Ao2BGT5EH5kGKgLTG0UXl40ghZhxTF_Xhhyjd1UzNqsU80--7EwGF_2R3nFLShFNCSUG6u5021Xqzqelst_1DeZoFMiQ</recordid><startdate>20160308</startdate><enddate>20160308</enddate><creator>NOZUE HIROSHI</creator><creator>SAKAMOTO HIROYUKI</creator><creator>KAWAGOME KAZUHIRO</creator><creator>MIYAGAWA MASAKI</creator><creator>NAKAI HIROTO</creator><creator>KUNIMATSU ATSUSHI</creator><creator>MAEDA KENICHI</creator><scope>EVB</scope></search><sort><creationdate>20160308</creationdate><title>Information processing device including memory management device managing access from processor to memory and memory management method</title><author>NOZUE HIROSHI ; SAKAMOTO HIROYUKI ; KAWAGOME KAZUHIRO ; MIYAGAWA MASAKI ; NAKAI HIROTO ; KUNIMATSU ATSUSHI ; MAEDA KENICHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9280466B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>NOZUE HIROSHI</creatorcontrib><creatorcontrib>SAKAMOTO HIROYUKI</creatorcontrib><creatorcontrib>KAWAGOME KAZUHIRO</creatorcontrib><creatorcontrib>MIYAGAWA MASAKI</creatorcontrib><creatorcontrib>NAKAI HIROTO</creatorcontrib><creatorcontrib>KUNIMATSU ATSUSHI</creatorcontrib><creatorcontrib>MAEDA KENICHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NOZUE HIROSHI</au><au>SAKAMOTO HIROYUKI</au><au>KAWAGOME KAZUHIRO</au><au>MIYAGAWA MASAKI</au><au>NAKAI HIROTO</au><au>KUNIMATSU ATSUSHI</au><au>MAEDA KENICHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Information processing device including memory management device managing access from processor to memory and memory management method</title><date>2016-03-08</date><risdate>2016</risdate><abstract>A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Information processing device including memory management device managing access from processor to memory and memory management method |
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