Detecting defective connections in stacked memory devices

A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value f...

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Bibliographische Detailangaben

Hauptverfasser:	SETHURAMAN SARAVANAN, KILMER CHARLES A, MAULE WARREN E
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES
Online-Zugang:	Volltext bestellen
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