Checkpoints associated with an out of order architecture

A checkpoint technique associated with an out of order based architecture of a processing device is described. An instruction may be received by its retirement unit and an identification as to whether the instruction is associated with a speculative error is performed. If the instruction is associat...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	KHARTIKOV DENIS M, KELM JOHN H, NEELAKANTAM NAVEEN
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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