Local voltage control for isolated transistor arrays

Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled...

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Hauptverfasser: NIERI RALPH CHRISTOPHER, PEACHEY NATHANIEL
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creator NIERI RALPH CHRISTOPHER
PEACHEY NATHANIEL
description Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9244478B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9244478B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9244478B23</originalsourceid><addsrcrecordid>eNrjZDDxyU9OzFEoy88pSUxPVUjOzyspys9RSMsvUsgszs9JLElNUSgpSswrziwuAYolFhUlVhbzMLCmJeYUp_JCaW4GBTfXEGcP3dSC_PjU4oLE5NS81JL40GBLIxMTE3MLJyNjIpQAAA7kLR4</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Local voltage control for isolated transistor arrays</title><source>esp@cenet</source><creator>NIERI RALPH CHRISTOPHER ; PEACHEY NATHANIEL</creator><creatorcontrib>NIERI RALPH CHRISTOPHER ; PEACHEY NATHANIEL</creatorcontrib><description>Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.</description><language>eng</language><subject>CONTROLLING ; PHYSICS ; REGULATING ; SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160126&amp;DB=EPODOC&amp;CC=US&amp;NR=9244478B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160126&amp;DB=EPODOC&amp;CC=US&amp;NR=9244478B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NIERI RALPH CHRISTOPHER</creatorcontrib><creatorcontrib>PEACHEY NATHANIEL</creatorcontrib><title>Local voltage control for isolated transistor arrays</title><description>Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.</description><subject>CONTROLLING</subject><subject>PHYSICS</subject><subject>REGULATING</subject><subject>SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDxyU9OzFEoy88pSUxPVUjOzyspys9RSMsvUsgszs9JLElNUSgpSswrziwuAYolFhUlVhbzMLCmJeYUp_JCaW4GBTfXEGcP3dSC_PjU4oLE5NS81JL40GBLIxMTE3MLJyNjIpQAAA7kLR4</recordid><startdate>20160126</startdate><enddate>20160126</enddate><creator>NIERI RALPH CHRISTOPHER</creator><creator>PEACHEY NATHANIEL</creator><scope>EVB</scope></search><sort><creationdate>20160126</creationdate><title>Local voltage control for isolated transistor arrays</title><author>NIERI RALPH CHRISTOPHER ; PEACHEY NATHANIEL</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9244478B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>CONTROLLING</topic><topic>PHYSICS</topic><topic>REGULATING</topic><topic>SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES</topic><toplevel>online_resources</toplevel><creatorcontrib>NIERI RALPH CHRISTOPHER</creatorcontrib><creatorcontrib>PEACHEY NATHANIEL</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NIERI RALPH CHRISTOPHER</au><au>PEACHEY NATHANIEL</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Local voltage control for isolated transistor arrays</title><date>2016-01-26</date><risdate>2016</risdate><abstract>Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.</abstract><oa>free_for_read</oa></addata></record>
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subjects CONTROLLING
PHYSICS
REGULATING
SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
title Local voltage control for isolated transistor arrays
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-08T09%3A48%3A16IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=NIERI%20RALPH%20CHRISTOPHER&rft.date=2016-01-26&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9244478B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true